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1. 发明申请

US20080195822A1 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的引导放置
公开(公告)号：US20080195822A1
公开(公告)日：2008-08-14
申请号：US12029134
申请日：2008-02-11
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

2. 发明授权

US08031526B1 Write pre-compensation for nonvolatile memory 有权
标题翻译：写入非易失性存储器的预补偿
公开(公告)号：US08031526B1
公开(公告)日：2011-10-04
申请号：US12196819
申请日：2008-08-22
申请人： Zining Wu , Xueshi Yang , Pantas Sutardja
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A memory integrated circuit (IC) includes an input that receives data for programming a target cell to a state. The memory IC further includes a programming module that determines a programming value for programming the target cell to the state based on the state and states of C cells that are adjacent to the target cell. The target cell and the C cells each store K bits per cell, where C and K are integers greater than or equal to 1.
摘要翻译：存储器集成电路（IC）包括接收用于将目标单元编程为状态的数据的输入。存储器IC还包括编程模块，其基于与目标单元相邻的C单元的状态和状态，确定用于将目标单元编程为状态的编程值。目标单元和C单元每个存储每个单元的K位，其中C和K是大于或等于1的整数。

3. 发明授权

US08407559B2 Monitoring memory 有权
标题翻译：监控内存
公开(公告)号：US08407559B2
公开(公告)日：2013-03-26
申请号：US12476683
申请日：2009-06-02
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G11C29/00
CPC分类号： G11C16/3404
摘要： Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory.
摘要翻译：描述了与监视存储器相关联的设备，系统，方法和其他实施例。在一个实施例中，一种方法确定与存储在闪速存储器中的一组数据相关联的第一数据质量。至少部分地基于第一数据质量，控制闪速存储器以校正该组数据以产生校正的数据集。校正的数据组被重新编程到闪存中。

4. 发明授权

US08358541B1 Write pre-compensation for nonvolatile memory 有权
标题翻译：写入非易失性存储器的预补偿
公开(公告)号：US08358541B1
公开(公告)日：2013-01-22
申请号：US13251822
申请日：2011-10-03
申请人： Zining Wu , Xueshi Yang , Pantas Sutardja
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A system including a programming module and an interference module. The programming module is configured to determine a programming value to which a state of a target cell is to be programmed, wherein the programming value is determined based on states of one or more cells near the target cell. The interference module is configured to generate interference values based on (i) the state of the target cell and (ii) the states of the one or more cells near the target cell. The programming module is further configured to determine the programming value based on at least one of the interference values selected according to (i) the state of the target cell and (ii) the states of the one or more cells near the target cell.
摘要翻译：一种包括编程模块和干扰模块的系统。编程模块被配置为确定要编程目标单元的状态的编程值，其中基于目标单元附近的一个或多个单元的状态来确定编程值。干扰模块被配置为基于（i）目标小区的状态和（ii）目标小区附近的一个或多个小区的状态来产生干扰值。编程模块还被配置为基于根据（i）目标小区的状态选择的干扰值和（ii）目标小区附近的一个或多个小区的状态中的至少一个来确定编程值。

5. 发明授权

US08316206B2 Pilot placement for non-volatile memory 有权
标题翻译：非易失性存储器的飞行员安置
公开(公告)号：US08316206B2
公开(公告)日：2012-11-20
申请号：US12029134
申请日：2008-02-11
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

6. 发明授权

US08583991B1 High density multi-level memory 有权
标题翻译：高密度多级存储器
公开(公告)号：US08583991B1
公开(公告)日：2013-11-12
申请号：US13542353
申请日：2012-07-05
申请人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
发明人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供了高密度，多级存储器。因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号值到内存块。可以描述和要求保护其他实施例。

7. 发明授权

US08386889B1 Drive replacement techniques for RAID systems 有权
标题翻译：驱动RAID系统的替代技术
公开(公告)号：US08386889B1
公开(公告)日：2013-02-26
申请号：US13454831
申请日：2012-04-24
申请人： Heng Tang , Zining Wu , Gregory Burd , Pantas Sutardja
发明人： Heng Tang , Zining Wu , Gregory Burd , Pantas Sutardja
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F11/08 , G06F11/1443 , G11C29/00 , H03M13/09 , H03M13/1515 , H03M13/155 , H03M13/611 , H03M13/618
摘要： A control module includes an encoder module, which generates a first code word for multiple drives. A detector module, in response to detecting an error in a first drive subsequent to generation of the first code word, initiates replacement of the first drive with a second drive. The encoder module generates a second code word for the second drive. A mapping module maps physical locations of data in the drives to logical locations of the first code word, assigns a predetermined value to one of the logical locations corresponding to the first drive to identify an unused logical location, and assigns the unused logical location to the second drive based on the predetermined value. A difference module generates a third code word based on the first and second code words. The encoder module generates an updated code word for the multiple drives based on the first and third code words.
摘要翻译：控制模块包括编码器模块，其生成用于多个驱动器的第一代码字。检测器模块响应于在产生第一代码字之后检测到第一驱动器中的错误，开始用第二驱动器替换第一驱动器。编码器模块为第二个驱动器生成第二个代码字。映射模块将驱动器中的数据的物理位置映射到第一码字的逻辑位置，将预定值分配给与第一驱动器对应的逻辑位置之一，以识别未使用的逻辑位置，并将未使用的逻辑位置分配给基于预定值的第二驱动。差分模块基于第一和第二码字产生第三码字。编码器模块基于第一和第三代码字产生用于多个驱动器的更新代码字。

8. 发明授权

US08219886B1 High density multi-level memory 有权
标题翻译：高密度多级存储器
公开(公告)号：US08219886B1
公开(公告)日：2012-07-10
申请号：US11614868
申请日：2006-12-21
申请人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
发明人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供了高密度，多级存储器。因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号值到内存块。可以描述和要求保护其他实施例。

9. 发明授权

US07836364B1 Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions 有权
标题翻译：用于使用保留单元来指示缺陷位置的电路，架构，设备，系统，方法，算法，软件和固件
公开(公告)号：US07836364B1
公开(公告)日：2010-11-16
申请号：US11789867
申请日：2007-04-25
申请人： Pantas Sutardja , Zining Wu
发明人： Pantas Sutardja , Zining Wu
IPC分类号： G11C29/00 , G11C7/00 , H03M13/00
CPC分类号： G06F11/167 , G06F11/1068 , G11C11/56 , G11C11/5621 , G11C16/349 , G11C29/00 , G11C2029/0411 , G11C2029/4402 , G11C2211/5641 , G11C2211/5646 , H03M13/09 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23
摘要： Circuits, architectures, systems, methods, algorithms, software and firmware for indicating positions of defective data storage cells using reserved (e.g., “pilot”) cells. The circuit generally includes a memory having multiple subunits, each subunit containing multiple data storage cells and at least one reserved cell. The reserved cells store information identifying whether one or more data storage cells in a subunit are defective. The method of identifying defective memory positions generally includes determining the status of data storage cells in a multi-subunit memory; storing such status information in a reserved cell; and reading the reserved cell. In various embodiments, the reserved cells differentiate between fewer voltage levels and/or store a lower density of information than the data storage cells. The present invention improves error correction capabilities using cells that are typically already available in many conventional nonvolatile memories. In some cases, marking data from defective cells as erasures effectively doubles the error correction capability of the system. When the reserved cells contain more than one level, the overhead for a given level of fault coverage decreases as a function of memory size.
摘要翻译：电路，架构，系统，方法，算法，软件和固件，用于指示使用保留（例如，“导频”）单元的缺陷数据存储单元的位置。电路通常包括具有多个子单元的存储器，每个子单元包含多个数据存储单元和至少一个保留单元。保留单元存储识别子单元中的一个或多个数据存储单元是否有缺陷的信息。识别缺陷存储器位置的方法通常包括确定多子存储器中的数据存储单元的状态; 将所述状态信息存储在保留小区中; 并读取保留的单元格。在各种实施例中，保留单元区分较少的电压电平和/或存储比数据存储单元更低密度的信息。本发明使用通常在许多常规非易失性存储器中可用的单元来提高纠错能力。在某些情况下，将来自有缺陷单元的数据标记为擦除有效地使系统的纠错能力增加一倍。当保留的小区包含多个级别时，给定级别的故障覆盖的开销作为内存大小的函数而减小。

10. 发明授权

US07715135B1 Methods, circuits, apparatus, and systems for read channel synchronization and/or fly height measurement 有权
标题翻译：用于读通道同步和/或飞高测量的方法，电路，装置和系统
公开(公告)号：US07715135B1
公开(公告)日：2010-05-11
申请号：US11453219
申请日：2006-06-13
申请人： Pantas Sutardja , Toai Doan , Zining Wu , Michael Madden
发明人： Pantas Sutardja , Toai Doan , Zining Wu , Michael Madden
IPC分类号： G11B20/14
CPC分类号： G11B20/1403 , G11B5/40 , G11B5/6005 , G11B5/6029 , G11B20/1217 , G11B2020/1232 , G11B2020/1287
摘要： Methods, circuits, and systems for processing a preamble field in a read channel (e.g., in a magnetic storage device such as a hard disk drive). The methods generally include the steps of (a) reading the preamble field, wherein the preamble field comprises a repetitive bit pattern having a logical transition every x bit periods, where x is an integer of at least 3 when d is 0 or 1, or where x is an integer of at least d+2 when d is greater than 1, and (b) processing the repetitive bit pattern. The methods may further relate to processing the preamble for synchronization with the read channel and/or for measuring the fly height of a read/write head. The invention also relates to methods of enabling read channel synchronization and/or fly height measurement. The circuitry for fly height measurement generally includes (a) reading logic configured to read a preamble field from a read channel, wherein the preamble field comprises a repetitive bit pattern, (b) determination logic configured to determine a characteristic of the repetitive bit pattern, and (c) correlation logic configured to correlate the characteristic to the fly height. The systems generally comprise those that include a circuit embodying one or more of the inventive concepts disclosed herein. The present invention advantageously provides improved resolution of signals resulting from the preamble fields and of harmonics of said signals, and enables fly height measurement and improved channel synchronization without consuming dedicated tracks, platters, etc. on a magnetic recording medium.
摘要翻译：用于处理读通道（例如，诸如硬盘驱动器的磁存储设备）中的前导码字段的方法，电路和系统。这些方法通常包括以下步骤：（a）读取前导字段，其中前导字段包括每x位周期具有逻辑转换的重复位模式，其中当d为0或1时x为至少3的整数，或其中当d大于1时x是至少d + 2的整数，以及（b）处理重复位模式。该方法还可以涉及处理与读取信道同步的前导码和/或用于测量读/写头的飞行高度。本发明还涉及使能读取通道同步和/或飞行高度测量的方法。用于飞行高度测量的电路通常包括（a）读取逻辑，其被配置为从读取通道读取前导码字段，其中前导码字段包括重复位模式，（b）确定逻辑，其被配置为确定重复位模式的特性，以及（c）相关逻辑，被配置为将特征与飞行高度相关联。系统通常包括包含体现本文公开的一个或多个发明构思的电路的系统。本发明有利地提供了由前导字段和所述信号的谐波产生的信号的改进的分辨率，并且使得能够进行飞行高度测量和改进的信道同步，而不需要在磁记录介质上消耗专用的轨道，拼盘等。

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