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1. 发明授权

US07679119B2 CMOS inverter based logic memory 有权
标题翻译：基于CMOS逆变器的逻辑存储器
公开(公告)号：US07679119B2
公开(公告)日：2010-03-16
申请号：US11936727
申请日：2007-11-07
申请人： Yakov Roizin , Victor Kairys , Erez Sarig , David Zfira
发明人： Yakov Roizin , Victor Kairys , Erez Sarig , David Zfira
IPC分类号： H01L29/94 , H01L27/092
CPC分类号： H01L27/115 , G11C16/0416 , G11C2216/10 , H01L27/11521
摘要： A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.
摘要翻译：用于移动应用的单单电可擦除/可编程CMOS逻辑存储器单元包括共享单个多晶硅浮置栅极的CMOS反相器，以及包括控制栅极电容器和可选的隔离P阱（IPW）电容器的增强型控制电容器，其形成于下面控制栅极电容。控制栅极电容器包括多晶硅控制栅极，该多晶硅控制栅极与浮置栅极交叉并用作电容器板以诱导Fowler-Nordheim（F-N）注入或带对带隧道（BBT）来编程和擦除浮动栅极。 IPW电容器通过IPW提供在控制栅极电容器下面的未使用的空间中，IPW通过电介质层与控制/浮动栅极分离并且电连接到控制栅极。 F-N注入和BBT编程/擦除均在5V或更低的条件下执行。

2. 发明申请

US20080135904A1 CMOS Inverter Based Logic Memory 有权
标题翻译：基于CMOS逆变器的逻辑存储器
公开(公告)号：US20080135904A1
公开(公告)日：2008-06-12
申请号：US11936727
申请日：2007-11-07
申请人： Yakov Roizin , Victor Kairys , Erez Sarig , David Zfira
发明人： Yakov Roizin , Victor Kairys , Erez Sarig , David Zfira
IPC分类号： H01L29/788 , H01L29/94
CPC分类号： H01L27/115 , G11C16/0416 , G11C2216/10 , H01L27/11521
摘要： A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.
摘要翻译：用于移动应用的单单电可擦除/可编程CMOS逻辑存储器单元包括共享单个多晶硅浮置栅极的CMOS反相器，以及包括控制栅极电容器和可选的隔离P阱（IPW）电容器的增强型控制电容器，其形成于下面控制栅极电容。控制栅极电容器包括多晶硅控制栅极，该多晶硅控制栅极与浮置栅极交叉并用作电容器板以诱导Fowler-Nordheim（F-N）注入或带对带隧道（BBT）来编程和擦除浮动栅极。 IPW电容器通过IPW提供在控制栅极电容器下面的未使用的空间中，IPW通过电介质层与控制/浮动栅极分离并且电连接到控制栅极。 F-N注入和BBT编程/擦除均在5V或更低的条件下执行。

3. 发明申请

US20110050874A1 CMOS Image Sensor Pixel Without Internal Sample/Hold Circuit 有权
标题翻译： CMOS图像传感器像素没有内部采样/保持电路
公开(公告)号：US20110050874A1
公开(公告)日：2011-03-03
申请号：US12553880
申请日：2009-09-03
申请人： Raz Reshef , Erez Sarig , Aviad Haber , Shay Alfassi , Guy Yehudian
发明人： Raz Reshef , Erez Sarig , Aviad Haber , Shay Alfassi , Guy Yehudian
IPC分类号： H04N7/18 , H04N5/335
CPC分类号： H04N5/374 , H04N5/3765 , H04N5/378
摘要： A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.
摘要翻译：例如用于内窥镜系统的非常小面积的CMOS图像传感器仅包括四个焊盘（电源，接地，数字输入，模拟输出），并且包括用于执行相关双采样（CDS）的4T像素阵列和相关联的控制电路，以产生与每个像素中的光电二极管检测到的光相关联的模拟复位电平和模拟信号电平值。代替处理芯片上的模拟值，模拟复位值和模拟信号值通过单个模拟接触焊盘一次以一行一行的形式发送，同时具有交错的同步信号，例如，内窥镜系统，其使用同步信号重建传感器的内部时钟，以处理模拟值。因此，结合CMOS图像传感器的内窥镜壳体仅需要四条线。

4. 发明申请

US20090179141A1 Horizontal Row Drivers For CMOS Image Sensor With Tiling On Three Edges 有权
标题翻译：用于CMOS图像传感器的水平行驱动器，具有三边平铺
公开(公告)号：US20090179141A1
公开(公告)日：2009-07-16
申请号：US12014070
申请日：2008-01-14
申请人： Erez Sarig , Raz Reshef , Shay Alfassi , David Cohen
发明人： Erez Sarig , Raz Reshef , Shay Alfassi , David Cohen
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14643
摘要： A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.
摘要翻译：通过平铺多个图像传感器管芯来创建大的图像传感器结构，其中每个图像传感器管芯包括延伸到管芯的三个边缘的像素阵列和沿着管芯的第四边缘设置的控制电路。访问像素阵列所需的控制电路（例如，没有行驱动电路）都不位于像素阵列中，从而使像素阵列间的像素间隔一致。由于每个图像传感器芯片的像素阵列延伸到裸片的三个边缘，每个图像传感器裸片的像素阵列可以与其他图像传感器芯片中的三个像素阵列相邻以形成具有2xN个平铺图像传感器芯片的大图像传感器结构。

5. 发明授权

US07280405B2 Integrator-based current sensing circuit for reading memory cells 有权
标题翻译：用于读取存储单元的基于积分器的电流检测电路
公开(公告)号：US07280405B2
公开(公告)日：2007-10-09
申请号：US11304168
申请日：2005-12-13
申请人： Erez Sarig
发明人： Erez Sarig
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/0491
摘要： Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a corresponding sense voltage. The amount of cell current (and resulting sense voltage) is controlled by the programmed/erased state of the NVM cell. The sense voltage is compared with a reference voltage to determine the cell's programmed/erased state. Current through neighbor cells is redirected to the sensing circuit using a special Y decoder to minimize the neighbor effect.
摘要翻译：通过向第一终端施加电位，将第二终端耦合到地，然后将第二终端去耦并将所得到的单元电流传递到一个非易失性存储器（NVM）单元，对所选择的NVM单元进行近地感测积分器，其产生相应的感测电压。电池电流的量（以及由此产生的感测电压）由NVM单元的编程/擦除状态控制。将感测电压与参考电压进行比较，以确定单元的编程/擦除状态。通过相邻小区的电流使用特殊的Y解码器重定向到感测电路，以最小化邻居效应。

6. 发明申请

US20060126389A1 Integrator-based current sensing circuit for reading memory cells 有权
标题翻译：用于读取存储单元的基于积分器的电流检测电路
公开(公告)号：US20060126389A1
公开(公告)日：2006-06-15
申请号：US11304168
申请日：2005-12-13
申请人： Erez Sarig
发明人： Erez Sarig
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/0491
摘要： Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a corresponding sense voltage. The amount of cell current (and resulting sense voltage) is controlled by the programmed/erased state of the NVM cell. The sense voltage is compared with a reference voltage to determine the cell's programmed/erased state. Current through neighbor cells is redirected to the sensing circuit using a special Y decoder to minimize the neighbor effect.
摘要翻译：通过向第一终端施加电位，将第二终端耦合到地，然后将第二终端去耦并将所得到的单元电流传递到一个非易失性存储器（NVM）单元，对所选择的NVM单元进行近地感测积分器，其产生相应的感测电压。电池电流的量（以及由此产生的感测电压）由NVM单元的编程/擦除状态控制。将感测电压与参考电压进行比较，以确定单元的编程/擦除状态。通过相邻小区的电流使用特殊的Y解码器重定向到感测电路，以最小化邻居效应。

7. 发明授权

US08520100B2 CMOS image sensor pixel without internal sample/hold circuit 有权
标题翻译： CMOS图像传感器像素，无内部采样/保持电路
公开(公告)号：US08520100B2
公开(公告)日：2013-08-27
申请号：US12553880
申请日：2009-09-03
申请人： Raz Reshef , Erez Sarig , Aviad Haber , Shay Alfassi , Guy Yehudian
发明人： Raz Reshef , Erez Sarig , Aviad Haber , Shay Alfassi , Guy Yehudian
IPC分类号： H04N5/217
CPC分类号： H04N5/374 , H04N5/3765 , H04N5/378
摘要： A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.
摘要翻译：例如用于内窥镜系统的非常小面积的CMOS图像传感器仅包括四个焊盘（电源，接地，数字输入，模拟输出），并且包括用于执行相关双采样（CDS）的4T像素阵列和相关联的控制电路，以产生与每个像素中的光电二极管检测到的光相关联的模拟复位电平和模拟信号电平值。代替处理芯片上的模拟值，模拟复位值和模拟信号值通过单个模拟接触焊盘一次以一行一行的形式发送，同时具有交错的同步信号，例如，内窥镜系统，其使用同步信号重建传感器的内部时钟，以处理模拟值。因此，结合CMOS图像传感器的内窥镜壳体仅需要四条线。

8. 发明申请

US20090033532A1 HIGH RESOLUTION COLUMN-BASED ANALOG-TO-DIGITAL CONVERTER WITH WIDE INPUT VOLTAGE RANGE FOR DENTAL X-RAY CMOS IMAGE SENSOR 有权
标题翻译：具有宽输入电压范围的高分辨率色谱柱的模拟数字转换器，用于牙科X射线CMOS图像传感器
公开(公告)号：US20090033532A1
公开(公告)日：2009-02-05
申请号：US11833770
申请日：2007-08-03
申请人： Raz Reshef , Erez Sarig , Shay Alfassi
发明人： Raz Reshef , Erez Sarig , Shay Alfassi
IPC分类号： H03M1/34 , H03M1/00
CPC分类号： H03M1/123 , H03M1/56 , H04N5/335 , H04N5/3742 , H04N5/378
摘要： An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.
摘要翻译：一种成像系统，包括列并行ADC，其响应于单个斜率总体斜坡信号和具有代表暗像素值的电压的匹配全局斜坡线信号而工作。匹配全局斜坡信号和匹配的全局斜坡线信号的信号路径以最小化噪声影响。在执行像素读取操作之前，全局斜坡信号通过第一电压范围（低于暗像素值）增加，以确保列并行ADC在线性范围内操作。可以调整第一个电压范围以消除与列并行ADC相关的偏移误差。列并联ADC提供在VDD和地之间具有全电压摆幅的输出信号。

9. 发明授权

US07479916B1 High resolution column-based analog-to-digital converter with wide input voltage range for dental X-ray CMOS image sensor 有权
标题翻译：高分辨率柱式模数转换器，具有宽输入电压范围，适用于牙科X射线CMOS图像传感器
公开(公告)号：US07479916B1
公开(公告)日：2009-01-20
申请号：US11833770
申请日：2007-08-03
申请人： Raz Reshef , Erez Sarig , Shay Alfassi
发明人： Raz Reshef , Erez Sarig , Shay Alfassi
IPC分类号： H03M1/56
CPC分类号： H03M1/123 , H03M1/56 , H04N5/335 , H04N5/3742 , H04N5/378
摘要： An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.
摘要翻译：一种成像系统，包括列并行ADC，其响应于单个斜率总体斜坡信号和具有代表暗像素值的电压的匹配全局斜坡线信号而工作。匹配全局斜坡信号和匹配的全局斜坡线信号的信号路径以最小化噪声影响。在执行像素读取操作之前，全局斜坡信号通过第一电压范围（低于暗像素值）增加，以确保列并行ADC在线性范围内操作。可以调整第一个电压范围以消除与列并行ADC相关的偏移误差。列并联ADC提供在VDD和地之间具有全电压摆幅的输出信号。

10. 发明申请

US20180301896A1 DEVICE AND METHOD FOR OVERCURRENT PROTECTION 审中-公开
公开(公告)号：US20180301896A1
公开(公告)日：2018-10-18
申请号：US15489910
申请日：2017-04-18
申请人： Alexander Faingersh , Valentin Lerner , Erez Sarig , Raz Reshef
发明人： Alexander Faingersh , Valentin Lerner , Erez Sarig , Raz Reshef
IPC分类号： H02H9/02
摘要： A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

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