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1. 发明授权

US08891599B2 Imaging apparatus, and transmission and reception apparatus 有权
标题翻译：成像装置，发送和接收装置
公开(公告)号：US08891599B2
公开(公告)日：2014-11-18
申请号：US13163902
申请日：2011-06-20
申请人： Yasuhiro Nakasha
发明人： Yasuhiro Nakasha
IPC分类号： H04B1/38 , G01S13/24 , G01S7/282 , G01S13/89
CPC分类号： G01S13/24 , G01S7/282 , G01S13/89
摘要： A transmission and reception apparatus includes: a transmitter circuit to transmit to an object a transmission signal including a comb-shaped wave in which a first plurality of pulses are arranged in a comb shape; and a receiver circuit to receive a reflection signal based on the transmission signal.
摘要翻译：发送和接收装置包括：发送器电路，向对象发送包括梳状波的发送信号，其中第一多个脉冲以梳状布置; 以及接收电路，用于基于发送信号接收反射信号。

2. 发明授权

US08054908B2 Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses 有权
标题翻译：用于通过使用脉冲通过无线电发送数据的发送器电路和无线电发送装置
公开(公告)号：US08054908B2
公开(公告)日：2011-11-08
申请号：US11987703
申请日：2007-12-04
申请人： Yasuhiro Nakasha , Yoichi Kawano
发明人： Yasuhiro Nakasha , Yoichi Kawano
IPC分类号： H04L27/00
CPC分类号： H04L27/04 , H04B1/71635 , H04B1/7172 , H04B1/7174 , H04L25/4902
摘要： A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.
摘要翻译：通过使用脉冲发送数据的发送器电路具有可变延迟电路和逻辑电路。可变延迟电路采用时钟作为输入，并根据数据延迟时钟。逻辑电路将时钟和可变延迟电路的输出作为输入，并通过在时钟和可变延迟电路的输出之间执行逻辑运算来输出脉冲。

3. 发明授权

US07612709B2 Radar device and processing method of the same 有权
标题翻译：雷达设备及其加工方法相同
公开(公告)号：US07612709B2
公开(公告)日：2009-11-03
申请号：US12175081
申请日：2008-07-17
申请人： Yoichi Kawano , Yasuhiro Nakasha
发明人： Yoichi Kawano , Yasuhiro Nakasha
IPC分类号： G01S13/08
CPC分类号： G01S13/10 , G01S7/282
摘要： A radar device has a clock generator (131) generating a base clock; a transmitter (121 to 125) transmitting transmission pulses as gradually increasing a displacement amount with respect to each edge of the base clock; and a receiver (101 to 106) receiving reflected waves of the transmitted transmission pulses in synchronization with the edges of the base clock.
摘要翻译：雷达装置具有产生基准时钟的时钟发生器（131）发送器（121至125），其相对于所述基本时钟的每个边缘逐渐增加位移量，发送发送脉冲; 以及与基准时钟的边沿同步地接收所发送的发送脉冲的反射波的接收器（101至106）。

4. 发明申请

US20080012660A1 Phase shifter circuit with proper broadband performance 有权
标题翻译：具有适当宽带性能的移相器电路
公开(公告)号：US20080012660A1
公开(公告)日：2008-01-17
申请号：US11606989
申请日：2006-12-01
申请人： Yasuhiro Nakasha , Tatsuya Hirose
发明人： Yasuhiro Nakasha , Tatsuya Hirose
IPC分类号： H03H7/18
CPC分类号： H03H7/21 , H03H7/185 , H03H7/19 , H03H2007/0192
摘要： A phase shifter circuit includes a plurality of first series circuits each comprised of a series connection of one capacitor and one resistor, a first circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of first series circuits in series, the first circuit element and the chain structure together constituting a first loop circuit, a plurality of second series circuits each comprised of a series connection of one capacitor and one resistor, a second circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of second series circuits in series, the second circuit element and the chain structure together constituting a second loop circuit, and a plurality of connection lines connecting between the first loop circuit and the second loop circuit.
摘要翻译：一种移相器电路包括多个第一串联电路，每个第一串联电路由一个电容器和一个电阻器的串联连接构成，第一电路元件至少包括电感，该电感连接在链结构的第一端和第二端之间，串联的第一串联电路，第一电路元件和链结构一起构成第一环路电路，多个第二串联电路，每个第二串联电路由一个电容器和一个电阻器的串联连接构成，第二电路元件至少包括电感连接在通过串联连接多个第二串联电路而制成的链结构的第一端和第二端之间，第二电路元件和链结构一起构成第二环路电路，以及多个连接线，其连接在第一环路电路和第二回路电路。

5. 发明申请

US20060114033A1 Sample -hold circuit 有权
标题翻译：采样电路
公开(公告)号：US20060114033A1
公开(公告)日：2006-06-01
申请号：US11076924
申请日：2005-03-11
申请人： Yasuhiro Nakasha , Tatsuya Hirose
发明人： Yasuhiro Nakasha , Tatsuya Hirose
IPC分类号： G11C27/02
CPC分类号： G11C27/028 , G11C27/02
摘要： A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.
摘要翻译：采样保持电路，其减小下垂并馈通，并且适用于高速操作，同时保持更宽的设计参数自由度，包括施加输入模拟信号的前置放大器，输出对应于在采样周期期间来自前置放大器的输出的变化，并且在由时钟信号的转变启动的保持时段期间保持与来自前置放大器的输出相对应的电压，以及连接到时钟信号的输出引脚的电流切换电路并且使得在采样周期期间流入前置放大器内的第一晶体管的电流流入另一个第二晶体管，以将恒定电位作为输入提供给核心部分。

6. 发明授权

US5390145A Resonance tunnel diode memory 失效
标题翻译：共振隧道二极管存储器
公开(公告)号：US5390145A
公开(公告)日：1995-02-14
申请号：US166108
申请日：1993-12-14
申请人： Yasuhiro Nakasha , Yuu Watanabe
发明人： Yasuhiro Nakasha , Yuu Watanabe
IPC分类号： G11C5/14 , G11C11/38 , G11C13/00
CPC分类号： G11C5/142 , G11C11/38 , G11C2211/5614
摘要： A semiconductor memory device including a plurality of bit lines and a plurality of word lines which intersect to form a matrix of cross points. A respective memory cell is disposed at each cross point and corresponds to the respective word line and respective bit line intersecting at the respective cross point. Each memory cell includes a transfer gate having a first current terminal connected to the corresponding bit line and a control terminal connected to the corresponding word line. Each memory cell also includes a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween. The interconnection node is connected to the second current terminal of the transfer gate. A characteristic controlling circuit is coupled to the plurality of bit lines and controls the voltage of each bit line based on whether a respective memory cell corresponding to the respective bit line is selected or not selected, the characteristic controlling circuit including a plurality of negative differential resistance elements respectively corresponding to the plurality of bit lines.
摘要翻译：一种半导体存储器件，包括多个位线和相交以形成交叉点矩阵的多个字线。相应的存储单元设置在每个交叉点处，并且对应于相应字线和在相应交叉点相交的相应位线。每个存储单元包括具有连接到对应位线的第一电流端子和连接到对应字线的控制端子的传输门。每个存储单元还包括一对串联连接的负差动电阻存储元件，其间具有互连节点。互连节点连接到传输门的第二电流端子。特征控制电路耦合到多个位线，并且基于是否选择对应于相应位线的相应存储单元来控制每个位线的电压，该特性控制电路包括多个负差分电阻分别对应于多个位线的元件。

7. 发明授权

US08437423B2 Transmission device 有权
标题翻译：传输设备
公开(公告)号：US08437423B2
公开(公告)日：2013-05-07
申请号：US12577289
申请日：2009-10-12
申请人： Yasuhiro Nakasha
发明人： Yasuhiro Nakasha
IPC分类号： H04L27/00
CPC分类号： H04L25/4902 , H03K5/06 , H04L27/02
摘要： A transmission device including a pulse generating section configured to generate a plurality of pulses using a signal of data and a signal obtained by delaying the signal of data, and to adjust the pulse width such that each of the plurality of pulses has a pulse width conforming to a sequence of the data; a band-pass filter filtering the plurality of pulses; and a transmission amplifier amplifying the filtered plurality of pulses and outputting the filtered plurality of pulses as a transmission signal.
摘要翻译：一种发送装置，包括：脉冲发生部，被配置为使用数据的信号和通过延迟数据的信号而获得的信号产生多个脉冲，并且调整脉冲宽度，使得所述多个脉冲中的每一个具有符合脉冲宽度到数据的序列; 滤波多个脉冲的带通滤波器; 以及发送放大器，放大经过滤波的多个脉冲，并将滤波的多个脉冲作为发送信号输出。

8. 发明授权

US08144761B2 Pulse transmission method, pulse transmission system, transmitter, and receiver 有权
标题翻译：脉冲传输方式，脉冲传输系统，发射机和接收机
公开(公告)号：US08144761B2
公开(公告)日：2012-03-27
申请号：US12238952
申请日：2008-09-26
申请人： Yasuhiro Nakasha
发明人： Yasuhiro Nakasha
IPC分类号： H04L27/00
CPC分类号： H04B1/7163 , H04B2001/6908 , H04L25/4902 , H04L25/4917
摘要： A pulse transmission method for transmitting data by using pulse signals, each having a predetermined pulse width; defining a symbol time at least N times the predetermined pulse width, N being at least 2; defining a basic delay time calculated by dividing the predetermined pulse width by a predetermined integer; placing the pulse signals in the symbol time by delaying the pulse signals by an integral multiple of the basic delay time from start of the symbol time, the number of the pulse signals being k and 0≦k≦N being satisfied; and transmitting the pulse signals.
摘要翻译：一种用于通过使用具有预定脉冲宽度的脉冲信号发送数据的脉冲发送方法; 将符号时间定义为至少预定脉冲宽度的N倍，N至少为2; 定义通过将预定脉冲宽度除以预定整数而计算的基本延迟时间; 通过将脉冲信号延迟从符号时间开始的基本延迟时间的整数倍，脉冲信号的数量为k和0＆nlE; k＆nlE; N被满足，将脉冲信号放在符号时间内; 并发送脉冲信号。

9. 发明申请

US20080204089A1 Dynamic frequency dividing circuit operating within limited frequency range 审中-公开
标题翻译：动态分频电路在有限频率范围内工作
公开(公告)号：US20080204089A1
公开(公告)日：2008-08-28
申请号：US11987702
申请日：2007-12-04
申请人： Yasuhiro Nakasha
发明人： Yasuhiro Nakasha
IPC分类号： H03B19/14
CPC分类号： H03B19/14
摘要： A frequency dividing circuit has a master circuit and a slave circuit, and a load section in at least either one of the master and slave circuits is constructed to provide an impedance that decreases with increasing frequency.
摘要翻译：分频电路具有主电路和从电路，并且主电路和从电路中的至少一个中的负载部分被构造成提供随频率增加而减小的阻抗。

10. 发明申请

US20080198939A1 Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses 有权
标题翻译：用于通过使用脉冲通过无线电发送数据的发送器电路和无线电发送装置
公开(公告)号：US20080198939A1
公开(公告)日：2008-08-21
申请号：US11987703
申请日：2007-12-04
申请人： Yasuhiro Nakasha , Yoichi Kawano
发明人： Yasuhiro Nakasha , Yoichi Kawano
IPC分类号： H04L27/00
CPC分类号： H04L27/04 , H04B1/71635 , H04B1/7172 , H04B1/7174 , H04L25/4902
摘要： A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.
摘要翻译：通过使用脉冲发送数据的发送器电路具有可变延迟电路和逻辑电路。可变延迟电路采用时钟作为输入，并根据数据延迟时钟。逻辑电路将时钟和可变延迟电路的输出作为输入，并通过在时钟和可变延迟电路的输出之间执行逻辑运算来输出脉冲。

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