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1. 发明授权

US07958338B2 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US07958338B2
公开(公告)日：2011-06-07
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

2. 发明申请

US20100095103A1 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US20100095103A1
公开(公告)日：2010-04-15
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

3. 发明授权

US08601239B2 Extended register addressing using prefix instruction 有权
标题翻译：使用前缀指令进行扩展寄存器寻址
公开(公告)号：US08601239B2
公开(公告)日：2013-12-03
申请号：US12827238
申请日：2010-06-30
申请人： Toshio Yoshida , Yasunobu Akizuki , Ryuichi Sunayama
发明人： Toshio Yoshida , Yasunobu Akizuki , Ryuichi Sunayama
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30101 , G06F9/30185
摘要： A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.
摘要翻译：处理器包括存储指令的存储单元，包括第一区域和第二区域的指令扩展信息寄存器，指令解码单元，其对包含第一扩展信息的第一前缀指令进行解码，所述第一前缀指令包括第一扩展信息，执行第一前缀指令，并且解码包括第一扩展信息的第二前缀指令和扩展紧跟在第二前缀指令的两个指令之后的指令的第二扩展信息;指令打包单元，其生成包括至少一个第一前缀指令或第二前缀指令的指令，以及当指令解码单元解码第一前缀指令或第二前缀指令时紧跟在第一前缀指令或第二前缀指令之后的指令，执行指令执行单元，剪切由指令包装单元生成的打包指令。

4. 发明授权

US08001362B2 Processing unit 有权
标题翻译：处理单元
公开(公告)号：US08001362B2
公开(公告)日：2011-08-16
申请号：US12633108
申请日：2009-12-08
申请人： Atsushi Fusejima , Takashi Suzuki , Toshio Yoshida , Yasunobu Akizuki
发明人： Atsushi Fusejima , Takashi Suzuki , Toshio Yoshida , Yasunobu Akizuki
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/3013 , G06F9/3857 , G06F11/3466 , G06F2201/88
摘要： A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
摘要翻译：处理单元包括多个线程执行单元，每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元，并且每个线程执行单元执行具有多个指令，用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器，并且执行用于完成包括在该线程中的指令的处理;线程选择装置，用于发送指令的提交事件涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。

5. 发明申请

US20110035572A1 Computing device, information processing apparatus, and method of controlling computing device 失效
标题翻译：计算设备，信息处理设备和控制计算设备的方法
公开(公告)号：US20110035572A1
公开(公告)日：2011-02-10
申请号：US12805476
申请日：2010-08-02
申请人： Yasunobu Akizuki , Toshio Yoshida
发明人： Yasunobu Akizuki , Toshio Yoshida
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/384 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.
摘要翻译：多个数据处理指令指示计算设备处理包括第一数据和第二数据的多个数据。当多重数据处理指令被解码时，选择两个可分配寄存器。一个用于存储由一个处理单元对第一数据执行的处理操作的结果，另一个用于存储由另一处理单元对第二数据执行的处理操作的结果。然后将那些存储的处理结果传送到结果寄存器。另一方面，正常数据处理指令指示关于第三数据的处理操作。当正常数据处理指令被解码时，选择一个可分配寄存器并用于存储处理单元对第三数据执行的处理结果。然后将存储的处理结果传送到结果寄存器。

6. 发明申请

US20100332802A1 Priority circuit, processor, and processing method 失效
标题翻译：优先级电路，处理器和处理方法
公开(公告)号：US20100332802A1
公开(公告)日：2010-12-30
申请号：US12801868
申请日：2010-06-29
申请人： Atsushi Fusejima , Yasunobu Akizuki , Toshio Yoshida
发明人： Atsushi Fusejima , Yasunobu Akizuki , Toshio Yoshida
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/3885 , G06F9/3891
摘要： A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.
摘要翻译：优先电路连接到保留站和处理不同的操作和调度的多个算术单元，当确定指示只能由特定算术单元执行指令的可执行标志被打开时，指令算术单元，其与特定运算单元不同，并且根据由指令解码器和保留站执行的输入，其队列空闲。

7. 发明申请

US20100095092A1 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US20100095092A1
公开(公告)日：2010-04-15
申请号：US12591994
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida
发明人： Yasunobu Akizuki , Toshio Yoshida
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed for a predetermined period during simultaneous multi-thread operation, and controls such that all the reservation stations (5, 6 and 7) can execute only a predetermined thread. Therefore if an entry that cannot be executed from the reservation stations (5, 6 and 7) exists, execution of an entry in the thread that cannot be executed can be enabled by stopping the execution of the thread which has been executed continuously.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。并且，指令执行控制装置具有线程选择电路（30），该线程选择电路（30）在同时进行多线程动作的同时检测指定尚未完成预定期间的状态，并且进行控制使得所有保留站（5,6,7））只能执行预定的线程。因此，如果存在不能从保留站（5,6）和7中执行的条目，则可以通过停止执行连续执行的线程来执行线程中不能执行的条目。

8. 发明申请

US20120246409A1 ARITHMETIC PROCESSING UNIT AND ARITHMETIC PROCESSING METHOD 审中-公开
标题翻译：算术处理单元和算术处理方法
公开(公告)号：US20120246409A1
公开(公告)日：2012-09-27
申请号：US13365324
申请日：2012-02-03
申请人： Yasunobu AKIZUKI , Toshio Yoshida
发明人： Yasunobu AKIZUKI , Toshio Yoshida
IPC分类号： G06F12/08
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3861
摘要： An arithmetic processing unit includes a cache memory, a register configured to hold data used for arithmetic processing, a correcting controller configured to detect an error in data retrieved from the register, a cache controller configured to access a cache area of a memory space via the cache memory or a noncache area of the memory space without using the cache memory in response to an instruction executing request for executing a requested instruction, and notify a report indicating that the requested instruction is a memory access instruction for accessing the noncache area, and an instruction executing controller configured to delay execution of other instructions subjected to error detection by the correcting controller while the cache controller executes the memory access instruction for accessing the noncache area when the instruction executing controller receives the notified report.
摘要翻译：算术处理单元包括高速缓冲存储器，配置为保存用于算术处理的数据的寄存器，配置为检测从寄存器检索的数据中的错误的校正控制器，配置为经由存储器存储器存储存储器空间的高速缓存区域的高速缓存控制器高速缓冲存储器或存储器空间的非缓冲区域，而不响应于执行请求指令的指令执行请求而不使用高速缓冲存储器，并且通知指示所请求的指令是用于访问非缓存区域的存储器访问指令的报告，以及指令执行控制器，其被配置为当所述指令执行控制器接收到通知的报告时，所述高速缓存控制器执行用于访问所述非缓存区域的存储器访问指令，来延迟由所述校正控制器执行错误检测的其他指令的执行。

9. 发明授权

US08438366B2 Allocating rename register from separate register sets for each result data of multiple data processing instruction 失效
标题翻译：为多个数据处理指令的每个结果数据，从单独的寄存器集分配重命名寄存器
公开(公告)号：US08438366B2
公开(公告)日：2013-05-07
申请号：US12805476
申请日：2010-08-02
申请人： Yasunobu Akizuki , Toshio Yoshida
发明人： Yasunobu Akizuki , Toshio Yoshida
IPC分类号： G06F9/345
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/384 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.
摘要翻译：多个数据处理指令指示计算设备处理包括第一数据和第二数据的多个数据。当多重数据处理指令被解码时，选择两个可分配寄存器。一个用于存储由一个处理单元对第一数据执行的处理操作的结果，另一个用于存储由另一处理单元对第二数据执行的处理操作的结果。然后将那些存储的处理结果传送到结果寄存器。另一方面，正常数据处理指令指示关于第三数据的处理操作。当正常数据处理指令被解码时，选择一个可分配寄存器并用于存储处理单元对第三数据执行的处理结果。然后将存储的处理结果传送到结果寄存器。

10. 发明授权

US08516223B2 Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit 失效
标题翻译：从保留站到备用运算单元空闲指令队列的调度指令
公开(公告)号：US08516223B2
公开(公告)日：2013-08-20
申请号：US12801868
申请日：2010-06-29
申请人： Atsushi Fusejima , Yasunobu Akizuki , Toshio Yoshida
发明人： Atsushi Fusejima , Yasunobu Akizuki , Toshio Yoshida
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/3885 , G06F9/3891
摘要： A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.
摘要翻译：优先电路连接到保留站和处理不同的操作和调度的多个算术单元，当确定指示只能由特定算术单元执行指令的可执行标志被打开时，指令算术单元，其与特定运算单元不同，并且根据由指令解码器和保留站执行的输入，其队列空闲。

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