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1. 发明授权

US08929151B2 Extended select gate lifetime 有权
标题翻译：扩展选择栅极寿命
公开(公告)号：US08929151B2
公开(公告)日：2015-01-06
申请号：US14313155
申请日：2014-06-24
申请人： Yogesh Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P Belgal
发明人： Yogesh Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P Belgal
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
摘要： A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.
摘要翻译：闪存器件可以包括在快闪存储器单元块中被组织为NAND串的两个或更多个闪存单元，以及在相对端耦合到NAND串的闪存单元，用作选择门。闪速存储器件可以能够向闪存控制器提供与选通门的电压阈值相关的信息，擦除响应于选择栅极擦除命令而用作选择栅极的闪存单元，以及编程用作响应于选择门程序命令选择门。闪存控制器可以耦合到闪存设备，并且如果闪存设备提供的信息指示至少一个选择门的电压阈值是如果由闪速存储器件提供的信息指示至少一个选择门的电压阈值在预定电压范围之外，则将选择门程序命令发送到闪速存储器件。

2. 发明申请

US20140307507A1 EXTENDED SELECT GATE LIFETIME 有权
标题翻译：扩展选择门锁生命
公开(公告)号：US20140307507A1
公开(公告)日：2014-10-16
申请号：US14313155
申请日：2014-06-24
申请人： Yogesh Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P. Belgal
发明人： Yogesh Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P. Belgal
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
摘要： A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.
摘要翻译：闪存器件可以包括在快闪存储器单元块中被组织为NAND串的两个或更多个闪存单元，以及在相对端耦合到NAND串的闪存单元，用作选择门。闪速存储器件可以能够向闪存控制器提供与选通门的电压阈值相关的信息，擦除响应于选择栅极擦除命令而用作选择栅极的闪存单元，以及编程用作响应于选择门程序命令选择门。闪存控制器可以耦合到闪存设备，并且如果闪存设备提供的信息指示至少一个选择门的电压阈值是如果由闪速存储器件提供的信息指示至少一个选择门的电压阈值在预定电压范围之外，则将选择门程序命令发送到闪速存储器件。

3. 发明授权

US08792283B2 Extended select gate lifetime 有权
标题翻译：扩展选择栅极寿命
公开(公告)号：US08792283B2
公开(公告)日：2014-07-29
申请号：US13528966
申请日：2012-06-21
申请人： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant Belgal
发明人： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant Belgal
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
摘要： A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.
摘要翻译：存储器件可以包括集成电路中的两个或更多个存储器单元，用作耦合到两个或更多个存储器单元的选择栅极的至少一个闪存单元以及接受选择栅极擦除命令和选择栅极程序指令的接口在集成电路正常运行期间。集成电路可以执行响应于选择栅极擦除命令擦除至少一个选择栅极的操作，并且响应于选择栅极程序命令编程至少一个选择栅极。

4. 发明申请

US20150092488A1 FLASH MEMORY SYSTEM ENDURANCE IMPROVEMENT USING TEMPERATURE BASED NAND SETTINGS 审中-公开
标题翻译：使用基于温度的NAND设置的闪存存储系统耐久性改进
公开(公告)号：US20150092488A1
公开(公告)日：2015-04-02
申请号：US14040239
申请日：2013-09-27
申请人： Yogesh Wakchaure , Kiran Pangal , Xin Guo
发明人： Yogesh Wakchaure , Kiran Pangal , Xin Guo
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C16/349 , G11C7/04 , G11C11/5628 , G11C16/26 , G11C16/3454
摘要： Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device. Other embodiments are also disclosed and claimed.
摘要翻译：描述了使用基于温度的闪存设置改善闪存系统耐久性的方法和装置。在一个实施例中，存储器控制器逻辑至少部分地基于阈值温度值和闪速存储器存储设备的感测温度的比较，将第一修剪简档或第二修剪简档中的一个应用于闪速存储器存储设备。还公开并要求保护其他实施例。

5. 发明申请

US20130343129A1 EXTENDED SELECT GATE LIFETIME 有权
标题翻译：扩展选择门锁生命
公开(公告)号：US20130343129A1
公开(公告)日：2013-12-26
申请号：US13528966
申请日：2012-06-21
申请人： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant Belgal
发明人： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant Belgal
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
摘要： A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.
摘要翻译：存储器件可以包括集成电路中的两个或更多个存储器单元，用作耦合到两个或更多个存储器单元的选择栅极的至少一个闪存单元以及接受选择栅极擦除命令和选择栅极程序指令的接口在集成电路正常运行期间。集成电路可以执行响应于选择栅极擦除命令擦除至少一个选择栅极的操作，并且响应于选择栅极程序命令编程至少一个选择栅极。

6. 发明授权

US09268631B2 Adaptive moving read references for memory cells 有权
标题翻译：存储单元的自适应移动读取参考
公开(公告)号：US09268631B2
公开(公告)日：2016-02-23
申请号：US13976463
申请日：2012-03-29
申请人： Lark-Hoon Leem , Kiran Pangal , Xin Guo
发明人： Lark-Hoon Leem , Kiran Pangal , Xin Guo
IPC分类号： G06F11/00 , G11C29/00 , G06F11/08 , G11C11/56 , G11C16/34 , G06F11/10
CPC分类号： G06F11/08 , G06F11/1048 , G11C11/5628 , G11C16/3418
摘要： Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed.
摘要翻译：公开了用于生成或提供用于从包括在存储设备中的非易失性存储器的一个或多个存储器单元的读取错误中恢复的移动读取参考（MRR）表的示例。可以将优先级自适应地分配给包括在MRR表中的条目，并且可以基于分配的优先级对条目进行排序使用。其他的例子被描述和要求保护。

7. 发明授权

US09047187B2 Defect management in memory systems 有权
标题翻译：内存系统缺陷管理
公开(公告)号：US09047187B2
公开(公告)日：2015-06-02
申请号：US13536861
申请日：2012-06-28
申请人： Xin Guo , Yogesh B. Wakchaure , Kiran Pangal , Hiroyuki Sanda
发明人： Xin Guo , Yogesh B. Wakchaure , Kiran Pangal , Hiroyuki Sanda
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10
CPC分类号： G06F11/073 , G06F11/0727 , G06F11/0793 , G06F11/1016 , G06F11/1068
摘要： Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.
摘要翻译：缺陷管理逻辑延长了存储系统的使用寿命。例如，如本文所讨论的，故障检测逻辑检测存储器系统中的故障的发生。缺陷管理逻辑确定失败的类型，例如失败是婴儿死亡型失败还是迟发型失败。根据故障类型，缺陷管理逻辑执行不同的操作以延长存储系统的使用寿命。例如，对于早期生活故障，缺陷管理逻辑可以将块的一部分包括故障退出。对于后期生活故障，由于读取/写入过多，故障管理逻辑可以将故障块从第一位单元存储密度模式转换为以每位存储单元存储密度模式运行。

8. 发明申请

US20140164863A1 ADAPTIVE MOVING READ REFERENCES FOR MEMORY CELLS 有权
标题翻译：自适应移动读存储器的参考
公开(公告)号：US20140164863A1
公开(公告)日：2014-06-12
申请号：US13976463
申请日：2012-03-29
申请人： Lark-Hoon Leem , Kiran Pangal , Xin Guo
发明人： Lark-Hoon Leem , Kiran Pangal , Xin Guo
IPC分类号： G06F11/08
CPC分类号： G06F11/08 , G06F11/1048 , G11C11/5628 , G11C16/3418
摘要： Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed.
摘要翻译：公开了用于生成或提供用于从包括在存储设备中的非易失性存储器的一个或多个存储器单元的读取错误中恢复的移动读取参考（MRR）表的示例。可以将优先级自适应地分配给包括在MRR表中的条目，并且可以基于分配的优先级对条目进行排序使用。其他的例子被描述和要求保护。

9. 发明申请

US20130268726A1 Dual Mode Write Non-Volatile Memory System 审中-公开
标题翻译：双模写非易失性存储器系统
公开(公告)号：US20130268726A1
公开(公告)日：2013-10-10
申请号：US13993596
申请日：2011-12-30
申请人： Xin Guo , Kiran Pangal , Paul D. Ruby , Feng Zhu
发明人： Xin Guo , Kiran Pangal , Paul D. Ruby , Feng Zhu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , Y02D70/126 , Y02D70/20
摘要： Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments.
摘要翻译：主机写入可能与对非易失性存储器系统的后台写操作不同。作为对主机写入和背景写入使用不同写入算法的结果，在一些实施例中可以提高最大系统寿命和最大系统性能。

10. 发明授权

US09543024B2 Nonvolatile memory erasure techniques 有权
标题翻译：非易失性存储器擦除技术
公开(公告)号：US09543024B2
公开(公告)日：2017-01-10
申请号：US13995145
申请日：2012-03-29
申请人： Hiroyuki Sanda , Kiran Pangal , Xin Guo , Kaoru Naganuma
发明人： Hiroyuki Sanda , Kiran Pangal , Xin Guo , Kaoru Naganuma
IPC分类号： G06F12/00 , G11C16/16 , G11C11/56 , G11C16/34 , G06F12/02
CPC分类号： G11C16/16 , G06F12/0246 , G11C11/5635 , G11C16/3445
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了在擦除之前非易失性存储器的条件预编程的方法，装置和系统配置。在一种情况下，该方法包括接收擦除非易失性存储器件的一部分中的信息的请求，其中该部分包括多个存储单元，确定包括在该部分中的多个存储单元中的一个或多个存储单元对所述非易失性存储器件进行编程，如果所述一个或多个存储单元被确定为被编程，并且擦除所述非易失性存储器件的预编程部分，则对所述非易失性存储器件的所述部分进行预编程。多个确定的编程存储单元可能不超过预定值。可以描述和/或要求保护其他实施例。

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