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1. 发明申请

US20110267124A1 CLOCK SIGNAL DUTY CORRECTION CIRCUIT 有权
标题翻译：时钟信号校正电路
公开(公告)号：US20110267124A1
公开(公告)日：2011-11-03
申请号：US12846669
申请日：2010-07-29
申请人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要翻译：时钟信号占空比校正电路包括：第一转移定时控制单元，被配置为通过使用时钟信号产生用于控制占空比校正时钟信号的上升定时的第一控制信号; 第二转移定时控制单元，被配置为通过使用根据代码信号的时钟信号来生成用于改变占空比校正时钟信号的下降定时的第二控制信号; 以及差分缓冲器单元，被配置为响应于所述第一控制信号和所述第二控制信号而生成其上升时间或下降时间被调整的占空比校正时钟信号。

2. 发明申请

US20120250402A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20120250402A1
公开(公告)日：2012-10-04
申请号：US13340755
申请日：2011-12-30
申请人： Taek Sang SONG , Dae Han KWON
发明人： Taek Sang SONG , Dae Han KWON
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C7/14 , G11C13/0004 , G11C13/004 , G11C2013/0045 , G11C2013/0054
摘要： A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.
摘要翻译：半导体存储装置包括电阻式存储单元; 数据感测单元，被配置为基于参考电压感测由提供给所述电阻性存储单元的感测电流形成的输出电压，以及输出具有与所述感测结果对应的值的数据; 以及参考电压产生单元，包括分别包括具有第一和第二电阻值的第一和第二电阻器的虚拟存储单元，并且被配置为输出由提供给虚拟存储单元的感测电流形成的电压作为参考电压。

3. 发明申请

US20120195153A1 SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体系统和半导体器件
公开(公告)号：US20120195153A1
公开(公告)日：2012-08-02
申请号：US13168071
申请日：2011-06-24
申请人： Dae Han KWON , Chang Kyu CHOI , Jun Woo LEE , Taek Sang SONG
发明人： Dae Han KWON , Chang Kyu CHOI , Jun Woo LEE , Taek Sang SONG
IPC分类号： G11C8/18
CPC分类号： G11C7/1066
摘要： A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other.
摘要翻译：半导体装置包括奇数数据时钟缓冲器组，被配置为维持或移位多相源时钟信号的相位，并输出第一多相时钟信号，偶数数据时钟缓冲器组被配置为维持或移位相位多相源时钟信号，并输出第二多相时钟信号，奇数数据输出缓冲器组被配置为响应于第一多相时钟信号驱动奇数数据，并将驱动数据输出到奇数数据焊盘组以及偶数数据输出缓冲器组，被配置为响应于第二多相时钟信号驱动偶数数据，并将驱动数据输出到偶数数据焊盘组，其中第一和第二多相时钟的时钟信号的相位信号彼此不同。

4. 发明申请

US20130135038A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130135038A1
公开(公告)日：2013-05-30
申请号：US13611298
申请日：2012-09-12
申请人： Ki Han KIM , Hyun Woo LEE , Dae Han KWON , Chul Woo KIM , Soo Bin LIM
发明人： Ki Han KIM , Hyun Woo LEE , Dae Han KWON , Chul Woo KIM , Soo Bin LIM
IPC分类号： G05F1/10
CPC分类号： H03K19/094 , H03K19/0013 , H03K19/09482
摘要： A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.
摘要翻译：一种半导体装置，包括电源改变单元。电源改变单元被配置为接收使能信号和电源电压，根据使能信号产生第一电压或第二电压，根据电平信号改变第二电压的电压电平，并且提供第一电压或第二电压作为内部电路的驱动电压，其中内部电路接收第一输入信号以输出第二输入信号。

5. 发明申请

US20110267112A1 OUTPUT DRIVER AND SEMICONDUCTOR APPARATUS HAVING THE SAME 有权
标题翻译：输出驱动器和具有相同功能的半导体器件
公开(公告)号：US20110267112A1
公开(公告)日：2011-11-03
申请号：US12983164
申请日：2010-12-31
申请人： Jun Woo LEE , Dae Han KWON , Taek Sang SONG
发明人： Jun Woo LEE , Dae Han KWON , Taek Sang SONG
IPC分类号： H03K3/00
CPC分类号： H03K19/018528
摘要： An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal.
摘要翻译：输出驱动器包括：上拉信号生成单元，被配置为控制第一数据的脉冲宽度并输出上拉预驱动信号; 下拉信号生成单元，被配置为控制第二数据的脉冲宽度并输出下拉预驱动信号; 上拉预驱动器单元，被配置为接收所述上拉预驱动信号并产生上拉主驱动信号; 配置成接收下拉预驱动信号并产生下拉主驱动信号的下拉预驱动器单元; 上拉主驱动器单元，被配置为根据上拉主驱动信号对输出节点进行充电; 以及配置成根据下拉主驱动信号对输出节点进行放电的下拉主驱动器单元。

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