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1. 发明授权

US08754668B2 Integrated circuit and a method for testing a multi-tap integrated circuit 有权
标题翻译：集成电路和多抽头集成电路的测试方法
公开(公告)号：US08754668B2
公开(公告)日：2014-06-17
申请号：US11719924
申请日：2004-11-22
申请人： Yossi Amon , Dimitri Akselrod , Eyal Segev
发明人： Yossi Amon , Dimitri Akselrod , Eyal Segev
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505
摘要： An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
摘要翻译：一种集成电路，包括用于定义测试路径的控制器，所述测试路径包括多个测试访问端口中的至少一个测试访问端口，其特征在于还包括用于绕过所述多个测试访问端口中的至少一个的至少一个多位旁路逻辑，以及用于影响测试路径的长度。方便地，无论测试路径的配置如何变化，测试路径的长度保持基本上固定。一种用于测试集成电路的方法，该方法包括跨越测试路径传播测试信号的阶段。而该方法的特征在于定义测试路径的配置的阶段，而测试路径包括至少一个测试访问端口和至少一个旁路访问逻辑中的至少一个组件; 而至少一个多位旁路逻辑绕过多个测试访问端口中的至少一个并影响测试路径的长度。

2. 发明申请

US20100019794A1 INTEGRATED CIRCUIT AND A METHOD FOR TESTING A MULTI-TAP INTEGRATED CIRCUIT 有权
标题翻译：集成电路和测试多点集成电路的方法
公开(公告)号：US20100019794A1
公开(公告)日：2010-01-28
申请号：US11719924
申请日：2004-11-22
申请人： Yossi Amon , Dimitri Akselrod , Eyal Segev
发明人： Yossi Amon , Dimitri Akselrod , Eyal Segev
IPC分类号： G01R31/02
CPC分类号： G01R31/318558 , G01R31/318505
摘要： An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
摘要翻译：一种集成电路，包括用于定义测试路径的控制器，所述测试路径包括多个测试访问端口中的至少一个测试访问端口，其特征在于还包括用于绕过所述多个测试访问端口中的至少一个的至少一个多位旁路逻辑，以及用于影响测试路径的长度。方便地，无论测试路径的配置如何变化，测试路径的长度保持基本上固定。一种用于测试集成电路的方法，该方法包括跨越测试路径传播测试信号的阶段。而该方法的特征在于定义测试路径的配置的阶段，而测试路径包括至少一个测试访问端口和至少一个旁路访问逻辑中的至少一个组件; 而至少一个多位旁路逻辑绕过多个测试访问端口中的至少一个并影响测试路径的长度。

3. 发明授权

US08379861B2 Integrated circuit and a method for secure testing 有权
标题翻译：集成电路和安全测试方法
公开(公告)号：US08379861B2
公开(公告)日：2013-02-19
申请号：US11719883
申请日：2004-11-22
申请人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
发明人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
IPC分类号： H04L9/00 , H04K1/00 , G06F21/00
CPC分类号： G01R31/31719 , G01R31/318555
摘要： An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry.A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.
摘要翻译：一种包括控制器和多个内部电路的集成电路，而集成电路的特征在于进一步包括安全模式确定单元，该安全模式确定单元包括用于从多个可能的安全模式中定义安全模式的多个一次可编程组件，而所选择的电路模式影响对内部电路的访问。一种用于测试集成电路的方法，所述方法包括：接收访问内部电路的请求; 并根据定义的安全模式响应请求; 而该方法的特征在于以多个安全模式定义调试电路的安全模式的阶段，而定义响应于多个一次可编程组件的至少一个状态。

4. 发明申请

US20090296933A1 INTEGRATED CIRCUIT AND A METHOD FOR SECURE TESTING 有权
标题翻译：集成电路和安全测试方法
公开(公告)号：US20090296933A1
公开(公告)日：2009-12-03
申请号：US11719883
申请日：2004-11-22
申请人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
发明人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
IPC分类号： G06F21/02 , H04L9/00 , G01R31/00 , G06F11/00
CPC分类号： G01R31/31719 , G01R31/318555
摘要： An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry.A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.
摘要翻译：一种包括控制器和多个内部电路的集成电路，而集成电路的特征在于进一步包括安全模式确定单元，该安全模式确定单元包括用于从多个可能的安全模式中定义安全模式的多个一次可编程组件，而所选择的电路模式影响对内部电路的访问。一种用于测试集成电路的方法，所述方法包括：接收访问内部电路的请求; 并根据定义的安全模式响应请求; 而该方法的特征在于以多个安全模式定义调试电路的安全模式的阶段，而定义响应于多个一次可编程组件的至少一个状态。

5. 发明申请

US20090171646A1 METHOD FOR ESTIMATING POWER CONSUMPTION 审中-公开
标题翻译：估计消耗电力的方法
公开(公告)号：US20090171646A1
公开(公告)日：2009-07-02
申请号：US11574495
申请日：2004-08-31
申请人： Michael Silbermintz , Dimitri Akselrod , Boris Bobrov , Michael Priel , Amihay Rabenu , Amir Sahar , Shiri Shem-Tov , Boris Shulman
发明人： Michael Silbermintz , Dimitri Akselrod , Boris Bobrov , Michael Priel , Amihay Rabenu , Amir Sahar , Shiri Shem-Tov , Boris Shulman
IPC分类号： G06G7/62
CPC分类号： G06F11/3616 , G06F2217/78
摘要： A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and altering, in response to the power consumption estimate, the certain software code or the modeled system. A method of determining a power consumption of a system that executed a software code, the method includes the stages of: providing a reduced instruction set representation of the software code; and calculating a power consumption estimate of a modeled system associated with an execution of the reduced instruction set representation of the software code.
摘要翻译：一种用于确定系统和软件配置的方法，包括：计算与某个软件代码的执行相关联的建模系统的功耗估计; 并且响应于功耗估计改变某些软件代码或建模的系统。一种确定执行软件代码的系统的功耗的方法，所述方法包括以下阶段：提供所述软件代码的精简指令集表示; 以及计算与执行所述软件代码的精简指令集表示相关联的建模系统的功耗估计。

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