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1. 发明授权

US08754668B2 Integrated circuit and a method for testing a multi-tap integrated circuit 有权
标题翻译：集成电路和多抽头集成电路的测试方法
公开(公告)号：US08754668B2
公开(公告)日：2014-06-17
申请号：US11719924
申请日：2004-11-22
申请人： Yossi Amon , Dimitri Akselrod , Eyal Segev
发明人： Yossi Amon , Dimitri Akselrod , Eyal Segev
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505
摘要： An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
摘要翻译：一种集成电路，包括用于定义测试路径的控制器，所述测试路径包括多个测试访问端口中的至少一个测试访问端口，其特征在于还包括用于绕过所述多个测试访问端口中的至少一个的至少一个多位旁路逻辑，以及用于影响测试路径的长度。方便地，无论测试路径的配置如何变化，测试路径的长度保持基本上固定。一种用于测试集成电路的方法，该方法包括跨越测试路径传播测试信号的阶段。而该方法的特征在于定义测试路径的配置的阶段，而测试路径包括至少一个测试访问端口和至少一个旁路访问逻辑中的至少一个组件; 而至少一个多位旁路逻辑绕过多个测试访问端口中的至少一个并影响测试路径的长度。

2. 发明授权

US09892088B2 Data processing system and method of controlling access to a shared memory unit 有权
公开(公告)号：US09892088B2
公开(公告)日：2018-02-13
申请号：US14358049
申请日：2011-11-24
申请人： Michael Staudenmaier , Yossi Amon , Vincent Aubineau
发明人： Michael Staudenmaier , Yossi Amon , Vincent Aubineau
IPC分类号： G06F3/00 , G06F5/00 , G06F15/173 , G06F9/50 , G06F12/084
CPC分类号： G06F15/17331 , G06F9/5083 , G06F12/084
摘要： A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

3. 发明申请

US20150324287A1 A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS 审中-公开
标题翻译：一种使用CPU缓存存储器进行非CPU相关任务的方法和装置
公开(公告)号：US20150324287A1
公开(公告)日：2015-11-12
申请号：US14655109
申请日：2013-01-09
申请人： Michael PRIEL , Yossi AMON , Boris SHULMAN , Leonid SMOLYANSKY , Michael ZARUBINSKY
发明人： MICHAEL PRIEL , YOSSI AMON , BORIS SHULMAN , LEONID SMOLYANSKY , MICHAEL ZARUBINSKY
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0897 , G06F2212/1052 , G06F2212/251 , G06F2212/6012 , Y02D10/13
摘要： There is provided a processor for use in a computing system, said processor including at least one Central Processing Unit (CPU), a cache memory coupled to the at least one CPU, and a control unit coupled to the cache memory and arranged to obscure the existing data in the CPU cache memory, and assign control of the CPU cache memory to at least one other entity within the computing system. There is also provided a method of using a CPU cache memory for non-CPU related tasks in a computing system.
摘要翻译：提供了一种用于计算系统的处理器，所述处理器包括至少一个中央处理单元（CPU），耦合到至少一个CPU的高速缓存存储器，以及耦合到高速缓存存储器并被布置成遮蔽 CPU高速缓冲存储器中的现有数据，并且将CPU缓存存储器的控制分配给计算系统内的至少一个其他实体。还提供了在计算系统中使用用于非CPU相关任务的CPU高速缓冲存储器的方法。

4. 发明申请

US20140289357A1 DATA PROCESSING SYSTEM AND METHOD OF CONTROLLING ACCESS TO A SHARED MEMORY UNIT 有权
标题翻译：数据处理系统和控制访问共享存储单元的方法
公开(公告)号：US20140289357A1
公开(公告)日：2014-09-25
申请号：US14358049
申请日：2011-11-24
申请人： Michael Staudenmaier , Yossi Amon , Vincent Aubineau
发明人： Michael Staudenmaier , Yossi Amon , Vincent Aubineau
IPC分类号： G06F15/173
CPC分类号： G06F15/17331 , G06F9/5083 , G06F12/084
摘要： A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.
摘要翻译：提出一种包括至少存储单元，连接到存储器单元的第一客户端和连接到存储器单元的第二客户端的数据处理系统。第一客户端可以包括第一存储器存取单元和信息单元。第一存储器存取单元可以以第一数据速率从存储器单元读取数据或将数据写入存储器单元。信息单元可以更新与第一数据速率的最小要求值相关的内部数据。第二客户端可以包括第二存储器存取单元和数据速率限制单元。第二存储器访问单元可以以第二数据速率从存储器单元读取数据或向存储器单元写入数据。数据速率限制单元可以根据内部数据来限制第二数据速率。第一存储器存取单元可以例如从存储器单元顺序地读取数据包，并且信息单元可以至少每个数据包来更新内部数据。还提出了一种控制对共享存储器单元的访问的方法。

5. 发明授权

US08379861B2 Integrated circuit and a method for secure testing 有权
标题翻译：集成电路和安全测试方法
公开(公告)号：US08379861B2
公开(公告)日：2013-02-19
申请号：US11719883
申请日：2004-11-22
申请人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
发明人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
IPC分类号： H04L9/00 , H04K1/00 , G06F21/00
CPC分类号： G01R31/31719 , G01R31/318555
摘要： An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry.A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.
摘要翻译：一种包括控制器和多个内部电路的集成电路，而集成电路的特征在于进一步包括安全模式确定单元，该安全模式确定单元包括用于从多个可能的安全模式中定义安全模式的多个一次可编程组件，而所选择的电路模式影响对内部电路的访问。一种用于测试集成电路的方法，所述方法包括：接收访问内部电路的请求; 并根据定义的安全模式响应请求; 而该方法的特征在于以多个安全模式定义调试电路的安全模式的阶段，而定义响应于多个一次可编程组件的至少一个状态。

6. 发明授权

US06275835B1 Finite impulse response filter and method 有权
标题翻译：有限脉冲响应滤波器及方法
公开(公告)号：US06275835B1
公开(公告)日：2001-08-14
申请号：US09251216
申请日：1999-02-16
申请人： Eran Pisek , Moshe Tarrab , Yossi Amon
发明人： Eran Pisek , Moshe Tarrab , Yossi Amon
IPC分类号： G06F1710
CPC分类号： H03H17/06
摘要： A finite impulse response filter (90) has a data memory bank (92, 350) for storing data vectors and a coefficient memory bank (91, 300) for storing coefficient vectors. Filtering is done by multiplying data words by coefficient words, and summing the results. The finite impulse response filter (90) operates in different modes, according to the type of data vector and coefficient vector. In two modes of operation consecutive elements of the data vector (360-369, 460-475) are stored in consecutive odd memory words (380, 382..396) within the data memory bank (92, 350). In other modes consecutive elements of the data vector are stored in consecutive memory words (380-397) in the data memory bank (92, 350). Consecutive coefficient vector elements (310-319, 410-419) are stored in the consecutive memory words (340-349) in coefficient memory bank (91, 300), wherein coefficient elements can be stored in reverse or forward order. The data memory bank (92, 350) is coupled to a data address generator (200) comprising of counter (209), two multiplexers (220, 222), a XOR gate (270) and an AND gate (290).
摘要翻译：有限冲击响应滤波器（90）具有用于存储数据矢量的数据存储体（92,350）和用于存储系数向量的系数存储器组（91,300）。通过将数据字乘以系数字来进行滤波，并对结果求和。有限脉冲响应滤波器（90）根据数据向量和系数向量的类型在不同的模式下工作。在两种操作模式中，数据向量（360-369,460-475）的连续元素被存储在数据存储体（92,350）内的连续奇数存储字（380,382 ... 396）中。在其他模式中，数据向量的连续元素存储在数据存储体（92,350）中的连续存储字（380-397）中。连续系数向量元素（310-319,410-419）存储在系数存储体（91,300）中的连续存储字（340-349）中，其中系数元素可以以反向或正向顺序存储。数据存储器组（92,350）耦合到包括计数器（209），两个多路复用器（220,222），异或门（270）和与门（290）的数据地址发生器（200）。

7. 发明授权

US6138204A Multi bus access memory 失效
标题翻译：多总线访问存储器
公开(公告)号：US6138204A
公开(公告)日：2000-10-24
申请号：US992466
申请日：1997-12-17
申请人： Yossi Amon , Moshe Tarrab , Eytan Engel
发明人： Yossi Amon , Moshe Tarrab , Eytan Engel
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1078
摘要： The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.
摘要翻译：本发明涉及用于存储/检索来自存储器的数据的存储器和方法，所述存储器和数据由不同实际字宽的至少两个不同数据使用访问。用于存储可寻址二进制数据的存储器包括组织成位阵列单元的行和列的数据存储器，行地址解码器和用于寻址所选行的位阵列单元的驱动器，用于驱动位阵列单元的选定列的列驱动器和总线开关端口，用于在具有第一总线字宽度p的数据存储器和第一数据总线之间选择性地传送数据，并且具有小于第一总线字宽度p的第二总线字宽度q的第二数据总线。

8. 发明授权

US5742621A Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor 失效
标题翻译：用于在数据处理系统中实现加法比较选择蝶形运算的方法及其指令
公开(公告)号：US5742621A
公开(公告)日：1998-04-21
申请号：US554329
申请日：1995-11-02
申请人： Yossi Amon , Natan Baron
发明人： Yossi Amon , Natan Baron
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H04L25/08
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/30101 , G06F9/30112 , H03M13/4107 , H03M13/4184 , H03M13/6569
摘要： A parallel data structure and a dedicated Viterbi shift left instruction minimize the number of clock cycles required for decoding a convolutionally encoded signal in a data processing system (20) in software. Specifically, the data structure and Viterbi shift left instruction reduce the number of clock cycles required for performing an add-compare-select butterfly operation. The add-compare-select butterfly operation is included in a DO loop in a plurality of instructions for executing a Viterbi decoding algorithm, and is repeated a predetermined number of times, for choosing the best path through a trellis diagram.
摘要翻译：并行数据结构和专用维特比移位左指令以软件最小化在数据处理系统（20）中解码卷积编码信号所需的时钟周期数。具体地说，数据结构和维特比左移指令减少执行加法比较选择蝶形运算所需的时钟周期数。加法比较选择蝶形运算被包括在用于执行维特比解码算法的多个指令中的DO循环中，并且重复预定次数，用于选择通过网格图的最佳路径。

9. 发明申请

US20100019794A1 INTEGRATED CIRCUIT AND A METHOD FOR TESTING A MULTI-TAP INTEGRATED CIRCUIT 有权
标题翻译：集成电路和测试多点集成电路的方法
公开(公告)号：US20100019794A1
公开(公告)日：2010-01-28
申请号：US11719924
申请日：2004-11-22
申请人： Yossi Amon , Dimitri Akselrod , Eyal Segev
发明人： Yossi Amon , Dimitri Akselrod , Eyal Segev
IPC分类号： G01R31/02
CPC分类号： G01R31/318558 , G01R31/318505
摘要： An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
摘要翻译：一种集成电路，包括用于定义测试路径的控制器，所述测试路径包括多个测试访问端口中的至少一个测试访问端口，其特征在于还包括用于绕过所述多个测试访问端口中的至少一个的至少一个多位旁路逻辑，以及用于影响测试路径的长度。方便地，无论测试路径的配置如何变化，测试路径的长度保持基本上固定。一种用于测试集成电路的方法，该方法包括跨越测试路径传播测试信号的阶段。而该方法的特征在于定义测试路径的配置的阶段，而测试路径包括至少一个测试访问端口和至少一个旁路访问逻辑中的至少一个组件; 而至少一个多位旁路逻辑绕过多个测试访问端口中的至少一个并影响测试路径的长度。

10. 发明申请

US20090296933A1 INTEGRATED CIRCUIT AND A METHOD FOR SECURE TESTING 有权
标题翻译：集成电路和安全测试方法
公开(公告)号：US20090296933A1
公开(公告)日：2009-12-03
申请号：US11719883
申请日：2004-11-22
申请人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
发明人： Dimitri Akselrod , Yossi Amon , Asaf Ashkenazi
IPC分类号： G06F21/02 , H04L9/00 , G01R31/00 , G06F11/00
CPC分类号： G01R31/31719 , G01R31/318555
摘要： An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry.A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.
摘要翻译：一种包括控制器和多个内部电路的集成电路，而集成电路的特征在于进一步包括安全模式确定单元，该安全模式确定单元包括用于从多个可能的安全模式中定义安全模式的多个一次可编程组件，而所选择的电路模式影响对内部电路的访问。一种用于测试集成电路的方法，所述方法包括：接收访问内部电路的请求; 并根据定义的安全模式响应请求; 而该方法的特征在于以多个安全模式定义调试电路的安全模式的阶段，而定义响应于多个一次可编程组件的至少一个状态。

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