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1. 发明授权

US08543843B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08543843B1
公开(公告)日：2013-09-24
申请号：US11933349
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F9/46
CPC分类号： G06F9/3851
摘要： A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.
摘要翻译：包括一个或多个物理核心的虚拟核心管理系统，包括与执行程序相关联的逻辑状态集合的虚拟核心以及被配置为将所述虚拟核心映射到所述一个或多个物理内核之一的虚拟核心管理组件基于电源管理的考虑。

2. 发明授权

US08225315B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
IPC分类号： G06F9/455 , G06F15/76
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译：一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。第一个虚拟内核映射到物理内核。虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到响应虚拟核心管理组件检测物理内核空闲的物理核心。

3. 发明授权

US07797512B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07797512B1
公开(公告)日：2010-09-14
申请号：US11933297
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/46
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.
摘要翻译：包括一个或多个物理核心和一个或多个虚拟核心的虚拟核心管理系统。每个虚拟核心分别包括与相应程序的执行相关联的逻辑状态的集合。虚拟核心管理系统还包括一个或多个中断控制器，其被配置为发送一个或多个中断信号以中断与一个或多个虚拟核心中的至少一个虚拟核心相关联的对应程序的执行;以及虚拟核心管理组件，至少一个虚拟内核到一个或多个物理核心中的一个，并将一个或多个中断信号路由到相应的物理核心。

4. 发明授权

US08281308B1 Virtual core remapping based on temperature 有权
标题翻译：基于温度的虚拟核心重映射
公开(公告)号：US08281308B1
公开(公告)日：2012-10-02
申请号：US11933199
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.
摘要翻译：包括第一物理核心和第二物理核心的虚拟核心管理系统以及包括与执行程序相关联的逻辑状态的集合的虚拟核心。虚拟核心管理系统还包括配置成感测第一物理核心的温度的第一温度传感器和被配置为感测第二物理核心的温度的第二温度传感器，以及配置成将虚拟核心映射到基于第一物理核心的温度和第二物理核心的温度中的至少一个的第一物理核心和第二物理核心之一。

5. 发明授权

US08219788B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08219788B1
公开(公告)日：2012-07-10
申请号：US11933267
申请日：2007-10-31
申请人： Yu Qing Cheng , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/00
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a first physical core having a first utilization constraint, a second physical core having a second utilization constraint, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a utilization indicator configured to measure a utilization of the first physical core with respect to the first utilization constraint and measure a utilization of the second physical core with respect to the second utilization constraint, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the utilization of the first physical core and the utilization of the second physical core.
摘要翻译：一种虚拟核心管理系统，包括具有第一利用约束的第一物理核心，具有第二利用约束的第二物理核心和包括与执行程序相关联的逻辑状态的集合的虚拟核心。所述虚拟核心管理系统还包括利用指示器，其被配置为测量所述第一物理核心相对于所述第一利用约束的利用率并且测量所述第二物理核心相对于所述第二利用约束的利用率，以及虚拟核心管理组件被配置为基于所述第一物理核心的利用和所述第二物理核心的利用中的至少一个来将所述虚拟核心映射到所述第一物理核心和所述第二物理核心之一。

6. 发明授权

US07533242B1 Prefetch hardware efficiency via prefetch hint instructions 有权
标题翻译：通过预取提示指令预取硬件效率
公开(公告)号：US07533242B1
公开(公告)日：2009-05-12
申请号：US11279880
申请日：2006-04-15
申请人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
发明人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
IPC分类号： G06F9/26
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F2212/1021 , G06F2212/6028
摘要： A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. The prefetch hints are directed to control operation of one or more hardware memory prefetcher units included in the processor, providing for increased efficiency in memory prefetching operations. The hints may optionally provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch. Thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. The hints may include any combination of specific pattern hints (one/two/N-dimensional strides, indirect, and indirect-stride), modifiers including sparse and region, and a prefetch-stop directive. The parameters may include any combination of a count, a priority and a ramp.
摘要翻译：软件代理装配在指令集架构中定义的预取提示指令或前缀，指令/前缀将预取提示信息传送到能够根据指令集架构执行指令的处理器。预取提示旨在控制包括在处理器中的一个或多个硬件存储器预取器单元的操作，从而提高存储器预取操作的效率。提示可以可选地提供描述存储器参考流量模式的参数的任何组合以搜索，何时开始搜索，何时终止预取，以及如何积极地预取。因此，硬件预取器能够进行改进的流量预测，使用减少的硬件资源提供更准确的结果。提示可以包括特定模式提示（一/二/ N维步幅，间接和间接步幅），包括稀疏和区域的修饰符以及预取停止指令的任何组合。这些参数可以包括计数，优先级和斜坡的任何组合。

7. 发明授权

US07389403B1 Adaptive computing ensemble microprocessor architecture 有权
标题翻译：自适应计算集成微处理器架构
公开(公告)号：US07389403B1
公开(公告)日：2008-06-17
申请号：US11277761
申请日：2006-03-29
申请人： Donald B. Alpert , John Gregory Favor , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Donald B. Alpert , John Gregory Favor , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30181 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： An Adaptive Computing Ensemble (ACE) includes a plurality of flexible computation units as well as an execution controller to allocate the units to Computing Ensembles (CEs) and to assign threads to the CEs. The units may be any combination of ACE-enabled units, including instruction fetch and decode units, integer execution and pipeline control units, floating-point execution units, segmentation units, special-purpose units, reconfigurable units, and memory units. Some of the units may be replicated, e.g. there may be a plurality of integer execution and pipeline control units. Some of the units may be present in a plurality of implementations, varying by performance, power usage, or both. The execution controller dynamically alters the allocation of units to threads in response to changing performance and power consumption observed behaviors and requirements. The execution controller also dynamically alters performance and power characteristics of the ACE-enabled units, according to the observed behaviors and requirements.
摘要翻译：自适应计算集合（ACE）包括多个灵活的计算单元以及将单元分配给计算集合（CE）并将线程分配给CE的执行控制器。单元可以是启用ACE的单元的任何组合，包括指令提取和解码单元，整数执行和流水线控制单元，浮点执行单元，分段单元，专用单元，可重配置单元和存储单元。一些单位可能被复制，例如可以存在多个整数执行和流水线控制单元。一些单元可以存在于由性能，功率使用或两者变化的多个实现中。响应于观察到的行为和要求的性能和功耗的变化，执行控制器动态地改变单元对线程的分配。执行控制器还根据观察到的行为和要求动态地改变启用ACE的单元的性能和功率特性。

8. 发明授权

US07516274B2 Power conservation via DRAM access reduction 有权
标题翻译：通过DRAM访问减少节电
公开(公告)号：US07516274B2
公开(公告)日：2009-04-07
申请号：US11351070
申请日：2006-02-09
申请人： Laurent R. Moll , Seungyoon Peter Song , Peter N. Glaskowsky , Yu Qing Cheng
发明人： Laurent R. Moll , Seungyoon Peter Song , Peter N. Glaskowsky , Yu Qing Cheng
IPC分类号： G06F13/00
CPC分类号： G06F12/0802 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0875 , G06F12/0888 , G06F13/1694 , G06F2212/1028 , G06F2212/2515 , Y02D10/13 , Y02D10/14
摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
摘要翻译：通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。在缓冲模式下，当CPU开始在低功耗状态下运行时，与缓存/微型缓存进行匹配的非缓存访问（例如由DMA设备产生的）与指定的物理地址范围匹配，而不是由存储器控制器和DRAM。缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。在一种使用场景中，保留在缓冲/微型缓存中的数据是以压缩格式维护的图形刷新数据。

9. 发明授权

US07958312B2 Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state 有权
标题翻译：小而高功效的缓存，可在处理器处于低功耗状态时为背景DMA设备提供数据
公开(公告)号：US07958312B2
公开(公告)日：2011-06-07
申请号：US11559069
申请日：2006-11-13
申请人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F1/3225 , G06F12/0802 , G06F12/0808 , G06F12/0864 , G06F12/0888 , G06F2212/1028 , G06F2212/6046 , Y02D10/13
摘要： Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
摘要翻译：当微处理器中的缓存数据由于任何或所有微处理器处于低电平状态时，微处理器中的高速缓存数据不可访问时，小型和功率高效的缓冲器/微型高速缓冲存储器源和接收器被选择指向微处理器的相干域中的存储器空间，电源状态不支持窥探。通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存的数据同步。或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。

10. 发明授权

US07904659B2 Power conservation via DRAM access reduction 有权
标题翻译：通过DRAM访问减少节电
公开(公告)号：US07904659B2
公开(公告)日：2011-03-08
申请号：US11559133
申请日：2006-11-13
申请人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0875 , G06F12/0888 , G06F13/1694 , G06F2212/1028 , G06F2212/2515 , Y02D10/13 , Y02D10/14
摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
摘要翻译：通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。在缓冲模式下，当CPU开始在低功耗状态下运行时，与缓存/微型缓存进行匹配的非缓存访问（例如由DMA设备产生的）与指定的物理地址范围匹配，而不是由存储器控制器和DRAM。缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。在一种使用场景中，保留在缓冲/微型缓存中的数据是以压缩格式维护的图形刷新数据。

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