专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08793426B2 Microcontroller with linear memory access in a banked memory 有权
标题翻译：具有线性存储器存取存储器的微控制器
公开(公告)号：US08793426B2
公开(公告)日：2014-07-29
申请号：US12701664
申请日：2010-02-08
申请人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
发明人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.
摘要翻译：微控制器具有分成多个存储体的数据存储器，用于向数据存储器提供地址的地址多路复用器，向地址多路复用器的第一输入端提供第一部分地址的指令寄存器，不是地址复用器的存储体选择寄存器映射到数据存储器，用于向地址多路复用器的第一输入提供第二部分地址，以及映射到数据存储器的多个特殊功能寄存器，其中多个特殊功能寄存器包括与第二个地址多路复用器的输入，并且其中数据存储器包括多个存储器组中的多于一个存储器组，其形成没有映射特殊功能寄存器的线性数据存储器块。

2. 发明授权

US08799552B2 Microcontroller with special banking instructions 有权
标题翻译：具有特殊银行指示的微控制器
公开(公告)号：US08799552B2
公开(公告)日：2014-08-05
申请号：US12701720
申请日：2010-02-08
申请人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
发明人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
摘要翻译：一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块，没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

3. 发明申请

US20100205346A1 MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS 有权
标题翻译：具有特殊银行指示的微控制器
公开(公告)号：US20100205346A1
公开(公告)日：2010-08-12
申请号：US12701720
申请日：2010-02-08
申请人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
发明人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
IPC分类号： G06F12/06
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
摘要翻译：一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块，没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

4. 发明申请

US20100205345A1 MICROCONTROLLER WITH LINEAR MEMORY ACCESS IN A BANKED MEMORY 有权
标题翻译：在银行存储器中具有线性记忆访问的微控制器
公开(公告)号：US20100205345A1
公开(公告)日：2010-08-12
申请号：US12701664
申请日：2010-02-08
申请人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
发明人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.
摘要翻译：微控制器具有分成多个存储体的数据存储器，用于向数据存储器提供地址的地址多路复用器，向地址多路复用器的第一输入端提供第一部分地址的指令寄存器，不是地址复用器的存储体选择寄存器映射到数据存储器，用于向地址多路复用器的第一输入提供第二部分地址，以及映射到数据存储器的多个特殊功能寄存器，其中多个特殊功能寄存器包括与第二个地址多路复用器的输入，并且其中数据存储器包括多个存储器组中的多于一个存储器组，其形成没有映射特殊功能寄存器的线性数据存储器块。

5. 发明申请

US20090144511A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20090144511A1
公开(公告)日：2009-06-04
申请号：US12147647
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/35
摘要： An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.
摘要翻译： n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。

6. 发明授权

US07996651B2 Enhanced microprocessor or microcontroller 有权
标题翻译：增强的微处理器或微控制器
公开(公告)号：US07996651B2
公开(公告)日：2011-08-09
申请号：US12147647
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F9/35
CPC分类号： G06F9/30181 , G06F9/35
摘要： An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.
摘要翻译： n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。

7. 发明授权

US08539210B2 Context switching with automatic saving of special function registers memory-mapped to all banks 有权
标题翻译：具有自动保存特殊功能寄存器的上下文切换，内存映射到所有存储区
公开(公告)号：US08539210B2
公开(公告)日：2013-09-17
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F9/48
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

8. 发明授权

US07996647B2 Enhanced microprocessor or microcontroller 有权
标题翻译：增强的微处理器或微控制器
公开(公告)号：US07996647B2
公开(公告)日：2011-08-09
申请号：US12178249
申请日：2008-07-23
申请人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
发明人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
IPC分类号： G06F12/02
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30138 , G06F9/342 , G06F12/06
摘要： A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
摘要翻译：处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续存储块。提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址转换为访问所述第二存储区域，使得通过该地址，多个第二存储区域形成连续线性存储器块。

9. 发明申请

US20090144481A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20090144481A1
公开(公告)日：2009-06-04
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F12/06
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

10. 发明申请

US20100023671A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20100023671A1
公开(公告)日：2010-01-28
申请号：US12178249
申请日：2008-07-23
申请人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
发明人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
IPC分类号： G06F12/02
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30138 , G06F9/342 , G06F12/06
摘要： A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
摘要翻译：处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续存储块。提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址转换为访问所述第二存储区域，使得通过该地址，多个第二存储区域形成连续线性存储器块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式