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1. 发明授权

US08407432B2 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP 失效
标题翻译：缓存一致性排序实现和CMP自适应LLC访问优先级控制
公开(公告)号：US08407432B2
公开(公告)日：2013-03-26
申请号：US11173917
申请日：2005-06-30
申请人： Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
发明人： Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
摘要翻译：公开了一种用于高速缓存一致性排序实现和自适应LLC访问优先级控制的方法和装置。一个实施例提供了解决多个内部CMP核心，内部窥探和外部窥探之间的最后一级高速缓存访问优先级的机制。另一实施例提供了用于在多核CMP系统中实现高速缓存一致性的机制。

2. 发明授权

US10031848B2 Method and apparatus for improving snooping performance in a multi-core multi-processor 有权
公开(公告)号：US10031848B2
公开(公告)日：2018-07-24
申请号：US11153031
申请日：2005-06-14
申请人： Krishnakanth V. Sistla , Yen-Cheng Liu , Zhong-Ning Cai
发明人： Krishnakanth V. Sistla , Yen-Cheng Liu , Zhong-Ning Cai
IPC分类号： G06F12/08 , G06F12/084 , G06F12/0811 , G06F12/0831
摘要： A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

3. 发明授权

US07360008B2 Enforcing global ordering through a caching bridge in a multicore multiprocessor system 有权
标题翻译：通过多核多处理器系统中的缓存桥来强化全局排序
公开(公告)号：US07360008B2
公开(公告)日：2008-04-15
申请号：US11026676
申请日：2004-12-30
申请人： Krishnakanth V. Sistla , Yen-Cheng Liu , Zhong-Ning Cai
发明人： Krishnakanth V. Sistla , Yen-Cheng Liu , Zhong-Ning Cai
IPC分类号： G06F13/36
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/082 , G06F12/0831
摘要： The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.
摘要翻译：本发明提供了一种在MCMP系统中实现系统互连和内部核心接口之间的全局排序的有效方式。特别是，系统互连，处理器请求和处理器请求完成上的侦听事务可能会触发相应的侦听事务并请求完成核心。在系统互连上观察事务的顺序可能会强制生成事务触发到核心的顺序。由于这种排序是在多个接口之间，所以称为全局排序。

4. 发明申请

US20070005909A1 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP 失效
标题翻译：缓存一致性排序实现和CMP自适应LLC访问优先级控制
公开(公告)号：US20070005909A1
公开(公告)日：2007-01-04
申请号：US11173917
申请日：2005-06-30
申请人： Zhong-Ning Cai , Krishnakanth Sistla , Yen-Cheng Liu , Jeffrey Gilbert
发明人： Zhong-Ning Cai , Krishnakanth Sistla , Yen-Cheng Liu , Jeffrey Gilbert
IPC分类号： G06F13/28
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
摘要翻译：公开了一种用于高速缓存一致性排序实现和自适应LLC访问优先级控制的方法和装置。一个实施例提供了解决多个内部CMP核心，内部窥探和外部窥探之间的最后一级高速缓存访问优先级的机制。另一实施例提供了用于在多核CMP系统中实现高速缓存一致性的机制。

5. 发明申请

US20070005899A1 Processing multicore evictions in a CMP multiprocessor 审中-公开
标题翻译：在CMP多处理器中处理多核驱逐
公开(公告)号：US20070005899A1
公开(公告)日：2007-01-04
申请号：US11173919
申请日：2005-06-30
申请人： Krishnakanth Sistla , Yen-Cheng Liu , Zhong-Ning Cai
发明人： Krishnakanth Sistla , Yen-Cheng Liu , Zhong-Ning Cai
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F12/0824 , G06F12/0811 , G06F12/084 , G06F12/12 , G06F2212/507
摘要： A method and apparatus for improving snooping performance is disclosed. One embodiment provides mechanisms for processing multi-core evictions in a multi-core inclusive shared cache processor. By using parallel eviction state machine, the latency of eviction processing is minimized. Another embodiment provides mechanisms for processing multi-core evictions in a multi-core inclusive shared cache processor in the presence of external conflicts.
摘要翻译：公开了一种用于提高窥探性能的方法和装置。一个实施例提供了用于在多核包含共享高速缓存处理器中处理多核驱逐的机制。通过使用并行驱逐状态机，驱逐处理的延迟最小化。另一实施例提供了在存在外部冲突的情况下在多核包容共享高速缓存处理器中处理多核驱逐的机制。

6. 发明申请

US20060282622A1 Method and apparatus for improving snooping performance in a multi-core multi-processor 审中-公开
标题翻译：在多核多处理器中提高窥探性能的方法和装置
公开(公告)号：US20060282622A1
公开(公告)日：2006-12-14
申请号：US11153031
申请日：2005-06-14
申请人： Krishnakanth Sistla , Yen-Cheng Liu , Zhong-Ning Cai
发明人： Krishnakanth Sistla , Yen-Cheng Liu , Zhong-Ning Cai
IPC分类号： G06F13/28
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0831
摘要： A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.
摘要翻译：公开了一种用于提高窥探性能的方法和装置。在一个实施例中，使用一个或多个内容可寻址匹配来确定发生地址冲突的地点和时间。根据定时，可以设置读请求或窥探请求以重试。在另一个实施例中，可以使用年龄订单矩阵来确定何时可以在相同时间段期间发出几个核心窥探请求，以便在该时间段期间可以处理窥探。

7. 发明授权

US07228387B2 Apparatus and method for an adaptive multiple line prefetcher 有权
标题翻译：一种自适应多线预取器的装置和方法
公开(公告)号：US07228387B2
公开(公告)日：2007-06-05
申请号：US10611619
申请日：2003-06-30
申请人： Zhong-Ning Cai , William G. Auld , Jeffrey D. Gilbert
发明人： Zhong-Ning Cai , William G. Auld , Jeffrey D. Gilbert
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.
摘要翻译：一种用于自适应多行预取的方法和装置。在一个实施例中，该方法包括识别预取深度。如本文所述，预取深度可以指要预取到临时（高速缓存）存储器的多条存储器线。一旦预取深度被识别，则根据所识别的预取深度来执行预取。在预取期间，当检测到预取深度的变化时，预取将被调整。因此，本文描述的动态自适应多线预取机制通过使用更有效的预取机制来促进更高的系统性能。

8. 发明授权

US09507534B2 Home agent multi-level NVM memory architecture 有权
标题翻译：家庭代理多级NVM内存架构
公开(公告)号：US09507534B2
公开(公告)日：2016-11-29
申请号：US13996668
申请日：2011-12-30
申请人： Dimitrios Ziakas , Zhong-Ning Cai
发明人： Dimitrios Ziakas , Zhong-Ning Cai
IPC分类号： G06F11/00 , G06F3/06 , G06F12/08
CPC分类号： G06F3/0619 , G06F3/0646 , G06F3/0683 , G06F12/08 , G06F12/0804 , G06F12/0811 , G06F2212/1028 , G06F2212/205 , Y02D10/13
摘要： Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.
摘要翻译：实现具有易失性存储器和非易失性存储器的多级存储器系统的系统和方法。归属代理可以控制对易失性主存储器和非易失性第二级存储器的存储器访问。第二级存储器可以包括主存储器。在一个实施例中，归属代理可以被配置为在低功率状态下管理存储器系统。在低功率状态下，可以关闭易失性存储器，并将非易失性存储器用作唯一的本地存储器。在一个实施例中，归属代理可以被配置为通过恢复在本地保存在第二级存储器中的数据来管理主存储器的错误恢复。在一个实施例中，多个核可以访问第二级存储器。

9. 发明授权

US06501999B1 Multi-processor mobile computer system having one processor integrated with a chipset 有权
标题翻译：具有与芯片组集成的一个处理器的多处理器移动计算机系统
公开(公告)号：US06501999B1
公开(公告)日：2002-12-31
申请号：US09470286
申请日：1999-12-22
申请人： Zhong-Ning Cai
发明人： Zhong-Ning Cai
IPC分类号： G05B902
CPC分类号： G06F1/3293 , G06F1/3203 , Y02D10/122 , Y02D10/126
摘要： Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.
摘要翻译：具有不同时钟频率和不同功耗水平的两个处理器的计算机系统。接口电路可以选择两个处理器中的一个来一次操作以降低功耗而不损害系统性能。

10. 发明授权

US06718475B2 Multi-processor mobile computer system having one processor integrated with a chipset 有权
标题翻译：具有与芯片组集成的一个处理器的多处理器移动计算机系统
公开(公告)号：US06718475B2
公开(公告)日：2004-04-06
申请号：US10306387
申请日：2002-11-27
申请人： Zhong-Ning Cai
发明人： Zhong-Ning Cai
IPC分类号： G06F132
CPC分类号： G06F1/3293 , G06F1/3203 , Y02D10/122 , Y02D10/126
摘要： Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.
摘要翻译：具有不同时钟频率和不同功耗水平的两个处理器的计算机系统。接口电路可以选择两个处理器中的一个来一次操作以降低功耗而不损害系统性能。

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