专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180101475A1 METHOD AND DEVICE FOR COMBINING ENTRIES IN DIRECTORY 审中-公开
公开(公告)号：US20180101475A1
公开(公告)日：2018-04-12
申请号：US15839665
申请日：2017-12-12
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Lei FANG , Xiongli GU , Weiguang CAI
IPC分类号： G06F12/0817 , G06F12/0808 , G06F12/084
CPC分类号： G06F12/0817 , G06F12/0808 , G06F12/082 , G06F12/084 , G06F12/121 , G06F2212/1021 , G06F2212/1044 , G06F2212/62
摘要： Embodiments of the present disclosure disclose a method for combining entries, including: determining N to-be-combined entries, where a cache block indicated by an entry label of each entry of the N entries belongs to a combination range, and the combination range indicates 2a cache blocks; and combining the N entries into a first entry, where an entry label of the first entry indicates the 2a cache blocks, and a sharer number of the first entry includes a sharer number of each entry of the N entries. According to the method, entries in a directory can be combined effectively, thereby improving directory usage efficiency.

2. 发明授权

US09594681B2 Dynamically configurable memory 有权
标题翻译：动态配置内存
公开(公告)号：US09594681B2
公开(公告)日：2017-03-14
申请号：US14853244
申请日：2015-09-14
申请人： Broadcom Corporation
发明人： David Matthew Lewsey
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02 , G06F11/14 , G06F13/00 , G06F3/06 , G06F12/06 , G06F1/26 , G06F1/32
CPC分类号： G06F12/0811 , G06F1/266 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F3/0625 , G06F11/1441 , G06F12/00 , G06F12/02 , G06F12/0223 , G06F12/0238 , G06F12/06 , G06F12/082 , G06F12/0846 , G06F12/0864 , G06F13/00 , G06F2201/86 , G06F2212/1028 , G06F2212/283 , G06F2212/601 , G06F2212/6032 , G06F2212/622 , G06F2212/7202 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A device includes a memory including ways and a processor in communication with the memory. The processor is configured to execute logic. The logic can monitor a parameter of the processor or a device connected with the processor. The logic can allocate, based on the parameter, a number a ways and a size of ways of the memory for use by the processor. The logic can power down an unallocated number of ways and unused portions of the ways of the memory.
摘要翻译：一种设备包括存储器，其包括与存储器通信的方式和处理器。处理器配置为执行逻辑。该逻辑可以监视处理器或与处理器连接的设备的参数。逻辑可以根据参数分配一些数量的方式和大小的存储器供处理器使用。该逻辑可以断开存储器方式的未分配数量的方式和未使用的部分。

3. 发明申请

US20170052890A1 OPERATION PROCESSING DEVICE AND METHOD FOR CONTROLLING OPERATION PROCESSING DEVICE 审中-公开
标题翻译：操作处理装置和控制操作处理装置的方法
公开(公告)号：US20170052890A1
公开(公告)日：2017-02-23
申请号：US15207974
申请日：2016-07-12
申请人： FUJITSU LIMITED
发明人： Junlu CHEN , Toru Hikichi
IPC分类号： G06F12/084 , G06F12/0808
CPC分类号： G06F12/084 , G06F12/0808 , G06F12/0811 , G06F12/082 , G06F12/128 , G06F2212/62
摘要： An operation processing device including: processors, first cache corresponding to each processors; and a second cache shared by the processors, wherein the second cache includes; a data retaining unit that retains data, a first information retaining unit that retains first management information of data in the first cache, a second information retaining unit that retains second management information of data in the data retaining unit, a classifying unit that classifies a request performed by referencing the first management information and not referencing the second management information as a first type request and classifies a request performed by referencing the second management information as a second type request, a second processing unit that references the second management information to perform the second type request, and a first processing unit that references the first management information and does not reference the second management information to perform the first type request.
摘要翻译：一种操作处理设备，包括：处理器，对应于每个处理器的第一高速缓存; 以及由所述处理器共享的第二高速缓存，其中所述第二高速缓存包括：保存数据的数据保持单元，保存第一高速缓存中的数据的第一管理信息的第一信息保持单元，将数据的第二管理信息保存在数据保持单元中的第二信息保持单元，对请求进行分类的分类单元通过参考第一管理信息而不引用第二管理信息作为第一类型请求，并将通过引用第二管理信息执行的请求分类为第二类型请求来执行;第二处理单元，其引用第二管理信息以执行第二管理信息以及第一处理单元，其引用第一管理信息，并且不引用第二管理信息来执行第一类型请求。

4. 发明授权

US09514047B2 Apparatus and method to dynamically expand associativity of a cache memory 有权
标题翻译：动态扩展高速缓冲存储器的关联性的装置和方法
公开(公告)号：US09514047B2
公开(公告)日：2016-12-06
申请号：US14573811
申请日：2014-12-17
申请人： Intel Corporation
发明人： Daniel Greenspan , Yoav Lossin , Blaise Fanning , Nagi Aboulenein , Marc Torrant
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/082 , G06F11/34 , G06F12/0607 , G06F12/0864 , G06F12/0895 , G06F2212/1016 , G06F2212/1021 , G06F2212/1028 , G06F2212/1044 , G06F2212/608 , Y02D10/13
摘要： In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心，高速缓存存储器和高速缓存控制器。响应于将数据条目的地址存储到高速缓冲存储器中的请求，高速缓存控制器将确定高速缓冲存储器的初始高速缓存集是否具有可用于存储该地址的容量。响应于初始高速缓存集中的容量不可用，高速缓存控制器将生成与数据条目相关联的第一备用地址，并且确定对应于第一备用地址的第一高速缓存集是否具有存储备用地址的可用容量，以及如果所以要将第一个备用地址存储在第一个缓存集中。描述和要求保护其他实施例。

5. 发明申请

US20160299857A1 Computer architecture with peripherals 审中-公开
标题翻译：具有外设的计算机架构
公开(公告)号：US20160299857A1
公开(公告)日：2016-10-13
申请号：US14997494
申请日：2016-01-16
申请人： Benjamin Aaron Gittins
发明人： Benjamin Aaron Gittins
IPC分类号： G06F13/20 , G06F13/40 , G06F12/08 , G06F13/16 , G11C7/10
CPC分类号： G06F13/364 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0831 , G06F12/0864 , G06F13/1663 , G06F13/20 , G06F13/372 , G06F13/4068 , G06F13/4282 , G06F2212/283 , G06F2212/6032 , G06F2212/621 , G11C7/1072
摘要： A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.
摘要翻译：具有系统互连，片上随机存取存储器（RAM），至少一个子计算设备和外围设备的共享存储器计算设备。 RAM连接到系统互连。每个子计算设备具有：（a）第一局部互连，（b）连接到子计算设备的局部互连的互连主机; 和（c）互连桥; 其中互连主机适于在该桥上向RAM发出存储器传送请求。所述外围设备包括目标端口，所述目标端口连接到所述至少一个子计算设备中的所述第一子计算设备的所述第一局部互连; 以及适于向RAM发出存储器传送请求的第一互连主端口。所述至少一个子计算设备中的第一个的互连主机适于向第一外设发出存储器传送请求。

6. 发明授权

US09400821B2 Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces 有权
标题翻译：存储器总线协议，以实现不同物理域地址空间的节点之间的聚类
公开(公告)号：US09400821B2
公开(公告)日：2016-07-26
申请号：US13838542
申请日：2013-03-15
申请人： Oracle International Corporation
发明人： Sanjiv Kapil , Zoran Radovic
IPC分类号： G06F15/173 , G06F17/30 , G06F9/54 , G06F9/38 , G06F12/08 , G06F12/12 , G06F12/14 , G06F21/62 , H04L29/06 , G06F15/78
CPC分类号： G06F9/30065 , G06F9/381 , G06F9/3851 , G06F9/3867 , G06F9/546 , G06F12/0804 , G06F12/082 , G06F12/12 , G06F12/1408 , G06F12/1475 , G06F13/102 , G06F13/362 , G06F13/4068 , G06F15/17331 , G06F15/7889 , G06F17/30324 , G06F17/30442 , G06F17/30483 , G06F17/30495 , G06F17/30498 , G06F17/30501 , G06F17/30519 , G06F17/30578 , G06F17/30595 , G06F17/30867 , G06F21/6209 , H04L69/14 , Y02D10/14 , Y02D10/151 , Y02D10/45
摘要： A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links. Each side of a link is coupled to a coprocessor which facilitates the movement of data between and among the nodes. Because each physical domain is separate from any other domain, the coprocessor in a physical domain uses a certificate, called and RKey, to obtain permission to transfer data to another physical domain. When an RKey is received from another physical domain, the coprocessor in the receiving domain validates the key and obtains the physical addresses associated with the key so that it can provide or accept the remote data. Data transfers between pairs of remote nodes in the cluster are permitted as well.
摘要翻译：公开了一种用于在群集中的节点之间传送数据和消息的系统和方法。集群中的每个节点都是单独的物理域，但通过点对点高速链路连接到集群中的其他节点。链路的每一侧被耦合到协处理器，这有助于数据在节点之间和之间的移动。由于每个物理域与任何其他域分开，物理域中的协处理器使用称为RKey的证书来获取将数据传输到另一个物理域的权限。当从另一个物理域接收到RKey时，接收域中的协处理器验证密钥并获得与密钥相关联的物理地址，以便它可以提供或接受远程数据。群集中的远程节点对之间的数据传输也被允许。

7. 发明授权

US09372813B2 Remote-key based memory buffer access control mechanism 有权
标题翻译：基于遥控键的内存缓冲存取控制机制
公开(公告)号：US09372813B2
公开(公告)日：2016-06-21
申请号：US13839525
申请日：2013-03-15
申请人： Oracle International Corporation
发明人： Sanjiv Kapil , Garret F. Swart , Aings Aingaran , William H. Bridge, Jr. , Sumti Jairath , John G. Johnson
IPC分类号： G06F12/00 , G06F13/10 , G06F17/30 , G06F9/54 , G06F9/38 , G06F12/08 , G06F12/12 , G06F15/173 , G06F12/14 , G06F21/62 , H04L29/06 , G06F15/78 , G06F13/362 , G06F13/40
CPC分类号： G06F9/30065 , G06F9/381 , G06F9/3851 , G06F9/3867 , G06F9/546 , G06F12/0804 , G06F12/082 , G06F12/12 , G06F12/1408 , G06F12/1475 , G06F13/102 , G06F13/362 , G06F13/4068 , G06F15/17331 , G06F15/7889 , G06F17/30324 , G06F17/30442 , G06F17/30483 , G06F17/30495 , G06F17/30498 , G06F17/30501 , G06F17/30519 , G06F17/30578 , G06F17/30595 , G06F17/30867 , G06F21/6209 , H04L69/14 , Y02D10/14 , Y02D10/151 , Y02D10/45
摘要： A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a local node coupled with a local memory. When it is determined that a selected base secret expired, the base secret stored in the register based on the base secret index is changed, thereby invalidating remote keys generated based on the expired base secret. A remote key with validation data and a base secret index is received from a node requesting access to the local memory. A validation base secret is obtained from the register based on the base secret index. The coprocessor performs hardware validation on the validation data based on the validation base secret. Hardware validation fails if the base secret associated with the base secret index has been changed in the register of the selected coprocessor.
摘要翻译：公开了一种实现可撤销的安全远程键的系统和方法。多个索引的基本秘密被存储在与本地存储器耦合的本地节点的协处理器的寄存器中。当确定所选择的基本秘密到期时，基于所述基本秘密索引存储在所述寄存器中的所述基本秘密被改变，从而使基于所述过期的基本秘密生成的远程密钥无效。从请求访问本地存储器的节点接收具有验证数据和基本秘密索引的远程密钥。基于基本秘密索引从寄存器获得验证基本密码。协处理器基于验证基础密码对验证数据执行硬件验证。如果在所选协处理器的寄存器中改变与基本秘密索引相关联的基本秘密，则硬件验证失败。

8. 发明授权

US09304929B2 Storage system having tag storage device with multiple tag entries associated with same data storage line for data recycling and related tag storage device 有权
标题翻译：具有标签存储装置的存储系统，具有与用于数据回收的相同数据存储线相关联的多个标签条目和相关标签存储装置
公开(公告)号：US09304929B2
公开(公告)日：2016-04-05
申请号：US14061765
申请日：2013-10-24
申请人： MediaTek Singapore Pte. Ltd.
发明人： Hsilin Huang
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/082 , G06F12/0851 , G06F12/0886 , G06F12/0895
摘要： A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.
摘要翻译：存储系统具有数据存储装置，标签存储装置和控制器。标签存储装置具有多个第一标签条目和多个第二标签条目，其中每个第一标签条目与分配在数据存储装置中的一个数据存储线路相关联。控制器耦合在数据存储装置和标签存储装置之间，并且被布置成在标签存储装置中设置特定的第二标签条目以与标签存储装置中的特定第一标签条目所在的特定数据存储线相关联相关联。

9. 发明授权

US09274961B2 Method for building multi-processor system with nodes having multiple cache coherency domains 有权
标题翻译：用于构建具有多个高速缓存一致性域的节点的多处理器系统的方法
公开(公告)号：US09274961B2
公开(公告)日：2016-03-01
申请号：US14534842
申请日：2014-11-06
申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD
发明人： Endong Wang , Leijun Hu , Jicheng Chen , Dong Zhang , Weifeng Gong , Feng Zhang
IPC分类号： G06F12/08 , G06F15/173
CPC分类号： G06F12/0822 , G06F12/082 , G06F12/0826 , G06F15/17368 , G06F2212/1016 , G06F2212/1048 , G06F2212/2542 , G06F2212/622
摘要： A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.
摘要翻译：一种用于构建具有多个高速缓存一致性域的节点的多处理器系统的方法。在该系统中，构建在节点控制器中的目录需要包括处理器域属性信息，并且可以通过配置连接到处理器的节点控制器的端口的高速缓存一致性域属性来获取信息。在本文的公开内容中，节点控制器可以支持节点中的多个物理高速缓存一致性域。

10. 发明授权

US09223711B2 Combining associativity and cuckoo hashing 有权
标题翻译：组合关联和杜鹃哈希
公开(公告)号：US09223711B2
公开(公告)日：2015-12-29
申请号：US13965668
申请日：2013-08-13
申请人： NETSPEED SYSTEMS
发明人： Joji Philip , Sailesh Kumar , Joe Rowlands
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/082
摘要： Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way Ci is a set-associative table with N sets, where each set has an associativity of A, where A is an integer greater than or equal to 2.
摘要翻译：与密钥相关的其他相关活动的添加，搜索和执行在硬件哈希表中执行。此外，可以为适用于CPU高速缓存和高速缓存一致性目录的散列表提供高性能和高效的设计。组合表和杜鹃散列相结合，用于构建基于目录的高速缓存一致性控制器的目录表。一种方法可以允许C布谷鸟方式的配置，其中C是大于或等于2的整数，其中每个布谷方式Ci是具有N个集合的集合关联表，其中每个集合具有A的关联性，其中A是大于或等于2的整数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式