会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Encoding methods and systems for binary product codes
    • 二进制产品代码的编码方法和系统
    • US08499219B2
    • 2013-07-30
    • US13324866
    • 2011-12-13
    • Zhongfeng Wang
    • Zhongfeng Wang
    • H03M13/00G06F11/00
    • H03M13/2909H03M13/152H03M13/1595H03M13/2903H03M13/6575
    • A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits. A multiplexer section multiplexes the blocks of source data, the serial row parity bits, and the serial column parity bits into an output stream including the blocks of source data encoded by the error correcting code.
    • 提供了数据编码电路和相应的方法。 数据编码电路包括与编码器部分通信的第一数据格式化器。 第一数据格式化器被配置为以串行方式接收源数据块并输出并行二维源数据。 编码器接收并行二维源数据,并且从平行二维源数据计算出纠错码的多个串行行奇偶校验位和多个并行列奇偶校验位。 第二数据格式化器与编码器部分通信并接收并行列奇偶校验位并输出串行列奇偶校验位。 多路复用器部分将源数据块,串行奇偶校验位和串行列奇偶校验位复用为包括由纠错码编码的源数据块的输出流。
    • 2. 发明授权
    • Forward error correction (FEC) scheme for communications
    • 用于通信的前向纠错(FEC)方案
    • US08341509B2
    • 2012-12-25
    • US12725887
    • 2010-03-17
    • Zhongfeng WangChung-Jue ChenKang Xiao
    • Zhongfeng WangChung-Jue ChenKang Xiao
    • G06F11/00
    • H03M13/2909H03M13/152H03M13/253H03M13/2903
    • Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing.
    • 用于通信的前向纠错(FEC)方案。 信息比特序列的比特的适当选择/排列经历一种或多种类型的后续编码,以生成可以随后经历适当处理以生成在通信信道内启动的连续时间信号的编码比特序列。 在一些实施例中,信息比特序列在被划分成多个信息比特组之后,首先经历第一编码模块内的第一编码,从而生成多个冗余/奇偶校验比特组(例如,每个冗余/奇偶校验位 组对应于一个信息位组)。 然后,在执行冗余/奇偶校验位组和信息位组内的位的任何期望和适当的选择/布置之后,在其上执行第二编码模块内的第二编码以产生附加的冗余/奇偶校验位。 此外,可以在编码处理的各个阶段执行交织。
    • 6. 发明申请
    • ENCODING METHODS AND SYSTEMS FOR BINARY PRODUCT CODES
    • 二进制编码的编码方法和系统
    • US20130147645A1
    • 2013-06-13
    • US13324866
    • 2011-12-13
    • Zhongfeng Wang
    • Zhongfeng Wang
    • H03M13/00
    • H03M13/2909H03M13/152H03M13/1595H03M13/2903H03M13/6575
    • A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits. A multiplexer section multiplexes the blocks of source data, the serial row parity bits, and the serial column parity bits into an output stream including the blocks of source data encoded by the error correcting code.
    • 提供了数据编码电路和相应的方法。 数据编码电路包括与编码器部分通信的第一数据格式化器。 第一数据格式化器被配置为以串行方式接收源数据块并输出并行二维源数据。 编码器接收并行二维源数据,并且从平行二维源数据计算出纠错码的多个串行行奇偶校验位和多个并行列奇偶校验位。 第二数据格式化器与编码器部分通信并接收并行列奇偶校验位并输出串行列奇偶校验位。 多路复用器部分将源数据块,串行奇偶校验位和串行列奇偶校验位复用为包括由纠错码编码的源数据块的输出流。