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1. 发明授权

US10750204B2 System and method for processing data 有权
公开(公告)号：US10750204B2
公开(公告)日：2020-08-18
申请号：US16205949
申请日：2018-11-30
申请人： ROZO SYSTEMS
发明人： Pierre Evenou , Didier Feron , Sylvain David , Jean-Pierre Monchanin
IPC分类号： H04N19/60 , G06F17/10 , H04N19/42 , H03M13/07 , H03M13/37 , H04N19/176 , H04N19/182
摘要： A processing system and method are provided for reconstituting a block of pixels from bins generated by a Mojette Transform, using a processing and calculation unit (UTC), a bin memory (MB), and a pixel memory (MP). The unit is configured to carry out the operations of reconstructing the pixels, which are performed by reading the bins in the bin memory, reading the reconstructed pixels in the pixel memory, and writing the reconstructed pixels in the pixel memory, such that the steps of reconstructing the pixels do not include an operation of writing bins in the bin memory.

2. 发明授权

US10291258B2 Error correcting code for correcting single symbol errors and detecting double bit errors 有权
公开(公告)号：US10291258B2
公开(公告)日：2019-05-14
申请号：US15605310
申请日：2017-05-25
申请人： Advanced Micro Devices, Inc.
发明人： Chin-Long Chen
IPC分类号： H03M13/11 , H03M13/00 , H03M13/15 , H03M13/07 , H03M13/03 , H03M13/13 , H03M13/19
摘要： Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N−2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of γ, wherein γ is equal to β raised to the (2m/4−1) power, β is equal to a raised to the (2m/2+1) power, and α is a primitive element of GF(2m). In another embodiment, the system receives a (N, N−2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

3. 发明申请

US20180288445A1 PICTURE CODING METHOD, PICTURE DECODING METHOD AND APPARATUSES THEREOF 审中-公开
公开(公告)号：US20180288445A1
公开(公告)日：2018-10-04
申请号：US16000299
申请日：2018-06-05
申请人： Panasonic Intellectual Property Corporation of America
发明人： Shinya KADONO , Makoto HAGAI
IPC分类号： H04N19/91 , H04N21/61 , H04N19/103 , H03M13/35 , H03M13/07 , H03M7/42 , H03M7/40 , H04N19/70 , H04N19/61 , H04N19/46 , H04L29/06 , H04N19/13 , H04N19/174 , H04N19/172 , H04N19/157 , H04N19/146 , H04N19/132 , H04N19/176 , H04N19/184
CPC分类号： H04N19/91 , H03M7/40 , H03M7/4006 , H03M7/42 , H03M13/07 , H03M13/35 , H04L65/607 , H04N19/103 , H04N19/13 , H04N19/132 , H04N19/146 , H04N19/157 , H04N19/172 , H04N19/174 , H04N19/176 , H04N19/184 , H04N19/46 , H04N19/61 , H04N19/70 , H04N21/6131
摘要： A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method and the frame stream, and constructs a picture coded signal.

4. 发明申请

US20180041780A1 PICTURE CODING METHOD, PICTURE DECODING METHOD AND APPARATUSES THEREOF 有权
公开(公告)号：US20180041780A1
公开(公告)日：2018-02-08
申请号：US15720259
申请日：2017-09-29
申请人： Panasonic Intellectual Property Corporation of America
发明人： Shinya KADONO , Makoto HAGAI
IPC分类号： H04N19/91 , H04N19/103 , H03M13/35 , H03M13/07 , H03M7/42 , H03M7/40 , H04N19/70 , H04N19/61 , H04N19/46 , H04L29/06 , H04N19/13 , H04N19/174 , H04N19/172 , H04N19/157 , H04N19/146 , H04N19/132 , H04N21/61 , H04N19/176 , H04N19/184
CPC分类号： H04N19/91 , H03M7/40 , H03M7/4006 , H03M7/42 , H03M13/07 , H03M13/35 , H04L65/607 , H04N19/103 , H04N19/13 , H04N19/132 , H04N19/146 , H04N19/157 , H04N19/172 , H04N19/174 , H04N19/176 , H04N19/184 , H04N19/46 , H04N19/61 , H04N19/70 , H04N21/6131
摘要： A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method the frame stream, and constructs a picture coded signal.

5. 发明授权

US09069687B2 Memory read-channel with selective transmission of error correction data 有权
标题翻译：存储器读通道，选择性地传输纠错数据
公开(公告)号：US09069687B2
公开(公告)日：2015-06-30
申请号：US12696572
申请日：2010-01-29
申请人： Nirav P. Dave , Nils Graef , Johnson Yen
发明人： Nirav P. Dave , Nils Graef , Johnson Yen
IPC分类号： H03M13/00 , G11C29/00 , G06F11/10 , H03M13/09 , H03M13/29 , H03M13/07 , H03M13/15
CPC分类号： G06F11/10 , H03M13/07 , H03M13/09 , H03M13/15 , H03M13/29
摘要： A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.
摘要翻译：存储器读通道被提供有错误校正数据的选择性传输。当不需要纠错码时，所公开的读通道提高了吞吐量并降低了功耗。从存储器件读取的数据包括用户数据，错误检测数据和纠错数据。在一个实施例中，评估错误检测数据以确定是否存在数据错误; 并且仅当检测到数据错误时才发送纠错数据。在另一个实施例中，在数据传输期间评估错误检测数据以确定是否存在数据错误，并且如果检测到数据错误则传输被暂停。通常，错误检测数据包括循环冗余校验，纠错数据包括奇偶校验数据。

6. 发明申请

US20130305127A1 FORWARD ERROR CORRECTION ENCODER 有权
标题翻译：前向纠错编码器
公开(公告)号：US20130305127A1
公开(公告)日：2013-11-14
申请号：US13468897
申请日：2012-05-10
申请人： Seuk B. Kim , Douglas E. Wente
发明人： Seuk B. Kim , Douglas E. Wente
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/151 , H03M13/09 , H03M13/31 , H04L1/0057 , H04L25/03866
摘要： A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width.
摘要翻译：提供了一种将数据字编码成帧的方法。在具有第一宽度的第一总线上接收输入数据字。输入数据字被缓冲以将中间数据字输出到具有第二宽度的第二总线上。从中间数据字生成转码位，并且使用校正子发生器从中间字生成一组奇偶位，其中校正子生成器使用等于第二宽度的位数。然后从中间数据字和奇偶校验位集合生成帧，并将其输出到具有第一宽度的第三总线。

7. 发明申请

US20130232396A1 APPARATUSES AND METHODS FOR ENCODING USING ERROR PROTECTION CODES 有权
标题翻译：使用错误保护代码编码的设备和方法
公开(公告)号：US20130232396A1
公开(公告)日：2013-09-05
申请号：US13412539
申请日：2012-03-05
申请人： Stephen P. Van Aken
发明人： Stephen P. Van Aken
IPC分类号： H03M13/05 , H03M13/07 , H03M13/15 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1076 , G11C29/52 , H03M13/15 , H03M13/151 , H03M13/1515 , H03M13/152 , H03M13/157 , H03M13/159 , H03M13/1595 , H04L1/0057
摘要： Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.
摘要翻译：本文公开的主题涉及存储在存储器件中和/或从存储器件读取的数据的错误保护。

8. 发明申请

US20130111304A1 CYCLIC CODE DECODING METHOD AND CYCLIC CODE DECODER 有权
标题翻译：循环码解码方法和循环码解码器
公开(公告)号：US20130111304A1
公开(公告)日：2013-05-02
申请号：US13609829
申请日：2012-09-11
申请人： Yi-Min Lin , Chih-Hsiang Hsu , Hsie-Chia Chang , Chen-Yi Lee
发明人： Yi-Min Lin , Chih-Hsiang Hsu , Hsie-Chia Chang , Chen-Yi Lee
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/152 , H03M13/1525 , H03M13/159 , H03M13/451 , H03M13/6502
摘要： In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to theELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.
摘要翻译：在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP，除此以外。

9. 发明申请

US20130061116A1 CONCURRENT DECODING OF DATA STREAMS 有权
标题翻译：数据流的同时解码
公开(公告)号：US20130061116A1
公开(公告)日：2013-03-07
申请号：US13565607
申请日：2012-08-02
申请人： Gary W. Grube , Timothy W. Markison
发明人： Gary W. Grube , Timothy W. Markison
IPC分类号： H03M13/05 , G06F11/10 , H03M13/07
CPC分类号： G06F11/10 , G06F17/30516 , H03M13/1148 , H03M13/616 , H04L65/607
摘要： A method begins by a dispersed storage (DS) processing module receiving one or more pairs of coded values. The method continues with the DS processing module creating a received coded matrix from the one or more pairs of coded values. When the received coded matrix includes a decode threshold number of pairs of coded values, the method continues with the DS processing module generating a data matrix from the received coded matrix and an encoding matrix, reproducing a one of a first plurality of data segments from a first plurality of data blocks of the data matrix, and reproducing a one of a second plurality of data segments from a second plurality of data blocks of the data matrix, wherein the one of the first plurality of data segments and the one of the second plurality of data segments maintain the time alignment of a first and second data streams.
摘要翻译：一种分散存储（DS）处理模块开始接收一对或多对编码值的方法。该方法继续DS处理模块从一个或多个编码值对创建接收的编码矩阵。当接收到的编码矩阵包括解码阈值数目的编码值对时，该方法继续DS处理模块从接收到的编码矩阵和编码矩阵生成数据矩阵，再现从第一多个数据段中的一个数据段数据矩阵的第一多个数据块，并且从数据矩阵的第二多个数据块再现第二多个数据段中的一个数据段，其中第一多个数据段中的一个和第二个多个数据块中的一个的数据段保持第一和第二数据流的时间对齐。

10. 发明申请

US20130055050A1 ERROR CORRECTION ENCODING APPARATUS, ERROR CORRECTION DECODING APPARATUS, NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM, AND PARITY CHECK MATRIX GENERATION METHOD 有权
标题翻译：错误校正编码设备，错误校正解码设备，非易失性半导体存储器系统和奇偶校验矩阵生成方法
公开(公告)号：US20130055050A1
公开(公告)日：2013-02-28
申请号：US13406808
申请日：2012-02-28
申请人： Hironori UCHIKAWA
发明人： Hironori UCHIKAWA
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/033 , G06F11/1012 , H03M13/09 , H03M13/116 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2906
摘要： According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification.
摘要翻译：根据一个实施例，纠错编码装置包括线性编码器和低密度奇偶校验（LDPC）编码器。线性编码器支持通过使用生成多项式的分割来执行奇偶校验的线性编码方案，并将生成多项式应用于输入数据以获得线性编码数据。 LDPC编码器将对应于LDPC码的奇偶校验矩阵的生成矩阵应用于线性编码数据以获得输出数据。奇偶校验矩阵满足说明书中所示的表达式（1）。

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