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1. 发明授权

US10181357B2 Code generating apparatus and one time programming block 有权
公开(公告)号：US10181357B2
公开(公告)日：2019-01-15
申请号：US15166277
申请日：2016-05-27
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Sung Yang , Ching-Hsiang Hsu
IPC分类号： G11C7/24 , G06F21/44 , G11C17/16 , G11C17/18 , G11C16/10
摘要： The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

2. 发明申请

US20170222817A1 Electronic Device with Self-protection and Anti-cloning Capabilities and Related Method 审中-公开
公开(公告)号：US20170222817A1
公开(公告)日：2017-08-03
申请号：US15423562
申请日：2017-02-02
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H04L9/32 , H04L9/08 , G06F12/14
CPC分类号： H04L9/3278 , G06F12/1408 , G06F21/445 , G06F21/73 , G06F21/85 , G06F2212/1052 , H04L9/0662 , H04L9/0866
摘要： An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).

3. 发明授权

US09466392B2 Memory array with memory cells arranged in pages 有权
标题翻译：内存单元格以页面排列
公开(公告)号：US09466392B2
公开(公告)日：2016-10-11
申请号：US14881177
申请日：2015-10-13
申请人： eMemory Technology Inc.
发明人： Wei-Chen Chang , Wen-Hao Ching , Chih-Hsin Chen , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C16/04 , G11C17/18 , G11C16/14 , G11C17/16 , H01L27/115 , H01L29/10 , H01L23/525 , H01L27/108 , H01L27/11 , H01L27/112 , H01L29/06 , H01L29/78 , H01L29/861 , H01L29/868 , G11C29/00
CPC分类号： G11C17/18 , G11C16/0408 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/14 , G11C17/16 , G11C29/785 , H01L23/5252 , H01L23/5256 , H01L27/10897 , H01L27/1116 , H01L27/11206 , H01L27/11524 , H01L27/1156 , H01L29/0649 , H01L29/1033 , H01L29/78 , H01L29/8611 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
摘要翻译：存储器阵列包括第一存储器页面和第二存储器页面。第一存储器页面包括第一字线，第一选择栅极线，第一控制线，第一擦除线和多个第一存储单元，每个第一存储单元耦合到第一字线，第一选择栅极线，第一控制线和第一擦除线，并用于接收位线信号和源极线信号。第二存储器页面包括第二控制线，第二擦除线和多个第二存储器单元，每个第二存储器单元耦合到第一字线，第一选择栅极线，第二控制线和第二擦除线，并且用于接收位线信号和源极线信号。

4. 发明申请

US20160104537A1 MEMORY ARRAY WITH MEMORY CELLS ARRANGED IN PAGES 有权
标题翻译：存储器阵列与存储器细胞安装在页面中
公开(公告)号：US20160104537A1
公开(公告)日：2016-04-14
申请号：US14881177
申请日：2015-10-13
申请人： eMemory Technology Inc.
发明人： Wei-Chen Chang , Wen-Hao Ching , Chih-Hsin Chen , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C17/18 , G11C16/0408 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/14 , G11C17/16 , G11C29/785 , H01L23/5252 , H01L23/5256 , H01L27/10897 , H01L27/1116 , H01L27/11206 , H01L27/11524 , H01L27/1156 , H01L29/0649 , H01L29/1033 , H01L29/78 , H01L29/8611 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
摘要翻译：存储器阵列包括第一存储器页面和第二存储器页面。第一存储器页面包括第一字线，第一选择栅极线，第一控制线，第一擦除线和多个第一存储单元，每个第一存储单元耦合到第一字线，第一选择栅极线，第一控制线和第一擦除线，并用于接收位线信号和源极线信号。第二存储器页面包括第二控制线，第二擦除线和多个第二存储器单元，每个第二存储器单元耦合到第一字线，第一选择栅极线，第二控制线和第二擦除线，并且用于接收位线信号和源极线信号。

5. 发明申请

US20190096497A1 CODE GENERATING APPARATUS AND ONE TIME PROGRAMMING BLOCK 审中-公开
公开(公告)号：US20190096497A1
公开(公告)日：2019-03-28
申请号：US16198884
申请日：2018-11-23
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Sung Yang , Ching-Hsiang Hsu
IPC分类号： G11C17/18 , G11C17/16 , G11C7/24 , G06F21/44
摘要： The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

6. 发明申请

US20170301406A1 Random number generator device and control method thereof 有权
公开(公告)号：US20170301406A1
公开(公告)日：2017-10-19
申请号：US15486310
申请日：2017-04-13
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： G11C17/18 , G11C17/16 , G06F7/58
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

7. 发明申请

US20160148686A1 MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES 审中-公开
标题翻译：电容随机存取存储器的存储单元阵列
公开(公告)号：US20160148686A1
公开(公告)日：2016-05-26
申请号：US14877239
申请日：2015-10-07
申请人： eMemory Technology Inc.
发明人： Chia-Jung Hsu , Wein-Town Sun , Ching-Sung Yang , Chi-Yi Shao , Chun-Yuan Lo , Yu-Hsiung Tsai , Ching-Yuan Lin
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0057 , G11C2013/0088 , G11C2213/78 , G11C2213/79 , G11C2213/82
摘要： A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.
摘要翻译：存储单元阵列包括第一位线，第一字线，第一源极线对和第一存储器单元。第一存储单元的选择端与第一字线连接。第一存储单元的第一控制端与第一源极线对的第一源极线连接。第一存储单元的第二控制端与第一源极线对的第二源极线连接。第一存储单元的第三控制端与第一位线连接。

8. 发明授权

US08604538B2 Non-volatile semiconductor memory device with intrinsic charge trapping layer 有权
公开(公告)号：US08604538B2
公开(公告)日：2013-12-10
申请号：US13726243
申请日：2012-12-24
申请人： eMemory Technology Inc.
发明人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42344
摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

9. 发明申请

US20130119458A1 NOR FLASH MEMORY CELL AND STRUCTURE THEREOF 审中-公开
公开(公告)号：US20130119458A1
公开(公告)日：2013-05-16
申请号：US13717725
申请日：2012-12-18
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Ching-Sung Yang
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0433 , H01L27/1157 , H01L29/518
摘要： The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a a substrate, an active area, a first gate structure, a second gate structure and at least one third gate structure. The first gate structure covers a first partial region of the active area and is formed by a silicon-rich nitride material. The second gate structure covers a second partial region of the active area. The third gate structure covers a third partial region between a first opening and the first gate structure. The active area has the first opening, the first opening disposed on a first side of the first gate structure and the first side is not neighbor to the second gate structure. The NOR flash memory cell further comprises a first conducting structure for covering the first opening to form a bit line signal receiving terminal.
摘要翻译：本发明提供了一种NOR闪存单元。 NOR闪存单元包括衬底，有源区，第一栅极结构，第二栅极结构和至少一个第三栅极结构。第一栅极结构覆盖有源区的第一部分区域并且由富含硅的氮化物材料形成。第二栅极结构覆盖有源区域的第二部分区域。第三栅极结构覆盖第一开口和第一栅极结构之间的第三部分区域。有源区域具有第一开口，第一开口设置在第一栅极结构的第一侧上，第一侧不邻近第二栅极结构。 NOR闪存单元还包括用于覆盖第一开口以形成位线信号接收端的第一导电结构。

10. 发明授权

US10020268B2 Random number generator device and control method thereof 有权
公开(公告)号：US10020268B2
公开(公告)日：2018-07-10
申请号：US15486310
申请日：2017-04-13
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： G11C17/00 , H01L23/00 , H01L23/522 , H01L27/088 , H01L29/06 , G11C16/14 , H01L27/11507 , H01L27/11529 , H01L29/423 , G06F7/58 , G11C17/16 , G11C17/18 , G11C16/04 , H01L27/11558 , H01L29/78
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

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