专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10797063B2 Single-poly nonvolatile memory unit 有权
公开(公告)号：US10797063B2
公开(公告)日：2020-10-06
申请号：US16231956
申请日：2018-12-25
申请人： eMemory Technology Inc.
发明人： Hsueh-Wei Chen , Wei-Ren Chen , Wein-Town Sun , Jui-Ming Kuo
IPC分类号： G11C5/06 , H01L27/11558 , H01L27/11524 , H01L29/06 , H01L29/423 , G11C16/26 , H01L29/788 , G11C16/04 , G11C16/14 , G11C16/10 , H01L27/11519
摘要： A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.

2. 发明授权

US09812212B2 Memory cell with low reading voltages 有权
公开(公告)号：US09812212B2
公开(公告)日：2017-11-07
申请号：US15408434
申请日：2017-01-18
申请人： eMemory Technology Inc.
发明人： Hsueh-Wei Chen , Wei-Ren Chen , Wein-Town Sun
IPC分类号： G11C16/04 , G11C16/26 , G11C16/14 , H01L27/11519
CPC分类号： H01L27/11558 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
摘要： A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

3. 发明申请

US20170207230A1 SINGLE-POLY NONVOLATILE MEMORY CELL STRUCTURE HAVING AN ERASE DEVICE 审中-公开
公开(公告)号：US20170207230A1
公开(公告)日：2017-07-20
申请号：US15384323
申请日：2016-12-20
申请人： eMemory Technology Inc.
发明人： Wein-Town Sun , Wei-Ren Chen , Ying-Je Chen
IPC分类号： H01L27/11558 , H01L29/06 , H01L29/423 , H01L29/08 , H01L29/10 , H01L27/12 , H01L27/11524
CPC分类号： H01L27/11558 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
摘要： A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.

4. 发明授权

US09601164B2 Array structure of single-ploy nonvolatile memory 有权
公开(公告)号：US09601164B2
公开(公告)日：2017-03-21
申请号：US15257292
申请日：2016-09-06
申请人： eMemory Technology Inc.
发明人： Wei-Ren Chen , Wen-Hao Lee
IPC分类号： G11C16/04 , G11C5/06 , G11C17/16 , H01L23/525 , H01L27/112 , H01L27/115
CPC分类号： G11C5/06 , G11C16/0408 , G11C16/0425 , G11C16/0433 , G11C16/10 , G11C16/14 , G11C16/26 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/528 , H01L27/11206 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11558 , H01L27/11573 , H01L29/0649 , H01L29/42328 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/7817 , H01L29/7835 , H01L29/93 , H01L2924/0002 , H01L2924/00
摘要： An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

5. 发明申请

US20160379687A1 ARRAY STRUCTURE OF SINGLE-PLOY NONVOLATILE MEMORY 有权
标题翻译：单层非易失性存储器的阵列结构
公开(公告)号：US20160379687A1
公开(公告)日：2016-12-29
申请号：US15257292
申请日：2016-09-06
申请人： eMemory Technology Inc.
发明人： Wei-Ren Chen , Wen-Hao Lee
IPC分类号： G11C5/06 , H01L27/115 , H01L23/525 , H01L27/112 , G11C16/04 , G11C17/16
CPC分类号： G11C5/06 , G11C16/0408 , G11C16/0425 , G11C16/0433 , G11C16/10 , G11C16/14 , G11C16/26 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/528 , H01L27/11206 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11558 , H01L27/11573 , H01L29/0649 , H01L29/42328 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/7817 , H01L29/7835 , H01L29/93 , H01L2924/0002 , H01L2924/00
摘要： An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.
摘要翻译：单聚多边形非易失性存储器的阵列结构包括第一MTP部分和第一OTP部分。第一MTP部分包括多个MTP单元，并且第一OTP部分包括多个OTP单元。第一MTP连接到第一字线，第一源极线，第一擦除线和多个位线。第一OTP部分连接到第二字线，第二源线和与第一MTP部分共享的多个位线。

6. 发明申请

US20150091074A1 NONVOLATILE MEMORY STRUCTURE 有权
标题翻译：非易失性存储器结构
公开(公告)号：US20150091074A1
公开(公告)日：2015-04-02
申请号：US14477818
申请日：2014-09-04
申请人： eMemory Technology Inc.
发明人： Te-Hsun Hsu , Wei-Ren Chen , Hsuen-Wei Chen , Mu-Ying Tsao , Ying-Je Chen
IPC分类号： H01L27/115 , H01L29/49 , H01L29/423
CPC分类号： H01L27/11558 , G11C5/147 , G11C7/12 , G11C16/0408 , G11C16/0433 , G11C16/28 , G11C16/30 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/4916
摘要： A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
摘要翻译：非易失性存储器结构包括P衬底，P衬底中的N阱和PMOS存储晶体管。 PMOS存储晶体管包括浮动栅极和设置在靠近浮置栅极的辅助栅极。浮置栅极和辅助栅极直接设置在PMOS存储晶体管的相同的浮置栅极沟道上。在辅助栅极和浮置栅极之间提供间隙，使得辅助栅极和浮置栅极至少在浮动栅极通道的正上方彼此分离。

7. 发明授权

US08779520B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08779520B2
公开(公告)日：2014-07-15
申请号：US13893794
申请日：2013-05-14
申请人： eMemory Technology Inc.
发明人： Wei-Ren Chen , Te-Hsun Hsu , Wen-Hao Lee
IPC分类号： H01L27/115 , H01L29/78
CPC分类号： H01L27/11517 , G11C16/10 , G11C2216/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：一种可擦除可编程单一多晶硅非易失性存储器，包括：基板结构; 具有浮置栅极的浮栅晶体管，浮置栅极下方的栅氧化层和沟道区，其中沟道区形成在N阱区中; 以及擦除栅极区，其中浮置栅极延伸到擦除栅极区域并且与擦除栅极区域相邻，并且擦除栅极区域包括连接到擦除线电压和P阱区域的n型源极/漏极区域。在衬底结构中形成N阱和P阱区。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

8. 发明授权

US11049564B2 Erasable programmable non-volatile memory 有权
公开(公告)号：US11049564B2
公开(公告)日：2021-06-29
申请号：US16803585
申请日：2020-02-27
申请人： eMemory Technology Inc.
发明人： Wein-Town Sun , Hsueh-Wei Chen , Chun-Hsiao Li , Wei-Ren Chen , Hong-Yi Liao
IPC分类号： G11C16/00 , G11C16/04 , G11C16/26 , G11C16/14 , H01L27/11521 , G11C16/10
摘要： An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

9. 发明申请

US20180019252A1 NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF 审中-公开
公开(公告)号：US20180019252A1
公开(公告)日：2018-01-18
申请号：US15648464
申请日：2017-07-13
申请人： eMemory Technology Inc.
发明人： Chun-Hsiao Li , Wei-Ren Chen , Wein-Town Sun
IPC分类号： H01L29/788 , H01L29/36 , H01L23/528 , H01L29/08 , H01L21/326 , H01L29/06 , H01L29/78 , H01L29/10
CPC分类号： H01L27/11524 , G11C7/04 , G11C7/1084 , G11C7/109 , G11C16/0433 , G11C16/12 , H01L21/326 , H01L23/528 , H01L27/11526 , H01L27/11548 , H01L29/0646 , H01L29/0688 , H01L29/0847 , H01L29/1095 , H01L29/36 , H01L29/7833 , H01L29/788 , H02M3/073 , H02M2001/007
摘要： A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

10. 发明申请

US20170207228A1 NONVOLATILE MEMORY STRUCTURE 审中-公开
公开(公告)号：US20170207228A1
公开(公告)日：2017-07-20
申请号：US15252244
申请日：2016-08-31
申请人： eMemory Technology Inc.
发明人： Ying-Je Chen , Wei-Ren Chen , Wein-Town Sun
IPC分类号： H01L27/115 , G11C16/04
CPC分类号： G11C16/30 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11558 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
摘要： A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region.The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式