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    • 3. 发明授权
    • Low capacitance chip varistor and fabrication method thereof
    • 低电容芯片变阻器及其制造方法
    • US6087923A
    • 2000-07-11
    • US40489
    • 1998-03-18
    • Byeung Joon AhnYong Joo Kim
    • Byeung Joon AhnYong Joo Kim
    • H01C7/12H01C10/00H01L7/10
    • H01C7/18H01C7/1006H01C7/108H01C7/112
    • A low capacitance chip varistor and a fabrication method thereof are described, which are capable of protecting the electronic elements of an electronic instrument from an external and internal surge and being well applicable to an electronic element which requires a low capacitance, and the low capacitance chip varistor includes at least one sheet support layer formed of a member having a low dielectric constant, a varistor layer including at least more than one varistor coating layer formed on the support layer, at least more than two internal electrode folded with a predetermined portion of the varistor layer to be connected with the varistor layer, one end of each of which is extended from a lateral surface of the support layer, and a pair of integrally formed external electrodes formed on a lateral surface of a varistor stack member integrally formed of the support layer, the varistor layer and the internal electrodes to be connected with one end portion of each internal electrode.
    • 描述了一种低电容芯片变阻器及其制造方法,其能够保护电子仪器的电子元件免受外部和内部浪涌,并且能够很好地应用于需要低电容的电子元件,而低电容芯片 变阻器包括由具有低介电常数的构件形成的至少一个片材支撑层,至少包括形成在支撑层上的至少一个压敏电阻涂层的至少一个压敏电阻层,至少两个内部电极, 压敏电阻层与压敏电阻层连接,其一端从支撑层的侧表面延伸,以及形成在由支撑体一体形成的可变电阻堆叠构件的侧表面上的一对整体形成的外部电极 层,可变电阻层和与每个内部电极的一个端部连接的内部电极 。
    • 4. 发明授权
    • Magnetic and dielectric composite electronic device
    • 磁介电复合电子器件
    • US07835135B2
    • 2010-11-16
    • US12040368
    • 2008-02-29
    • Kyoung Hwan ChoJung Ik SongJeong In Choi
    • Kyoung Hwan ChoJung Ik SongJeong In Choi
    • H01G4/06
    • H03H7/0107H01F1/344H01F17/0013H01F2017/0066H01G4/40H03H2001/0085
    • There is a provided a magnetic and dielectric composite electronic device, comprising: a first region with a plurality of magnetic material sheets being layered; a second region with a plurality of dielectric material sheets being layered; and a third region as a middle layer interposed between the first region and the second region, including a Zn—Ti based material to prevent diffusion of the materials during co-firing of the first region and the second region, and the first region, the second region and the third region are integrally formed in a single body. In accordance with the present invention, the low pass filter including the function of the varistor is realized to obtain the EMI function and the ESD control effect. Furthermore, the one chip electronic device having the composite functions is manufactured by a simple process, and the interdiffusion between the different materials forming the magnetic and the dielectric parts is prevented to secure the durability and electrical characteristics of the product.
    • 提供了一种磁性和电介质复合电子器件,包括:具有层叠有多个磁性材料片的第一区域; 具有层叠有多个介电材料片的第二区域; 以及插入在所述第一区域和所述第二区域之间的中间层的第三区域,包括Zn-Ti基材料,以防止在所述第一区域和所述第二区域的共烧期间所述材料的扩散,以及所述第一区域, 第二区域和第三区域一体地形成在单个主体中。 根据本发明,实现了包括变阻器功能的低通滤波器,以获得EMI功能和ESD控制效果。 此外,具有复合功能的单芯片电子器件通过简单的工艺制造,并且防止形成磁性材料和介电部件的不同材料之间的相互扩散以确保产品的耐久性和电气特性。
    • 5. 发明申请
    • Chip type power inductor and fabrication method thereof
    • 芯片型功率电感及其制造方法
    • US20040108934A1
    • 2004-06-10
    • US10723753
    • 2003-11-25
    • Ceratech Corporation
    • Myoung-Hui ChoiSoon-Gyu HongSang-Eun Jang
    • H01F005/00
    • H01F17/0013H01F41/046Y10T29/4902Y10T29/49069
    • A chip type power inductor comprising: a stack body where a magnetic substance which forms a magnetic core stacked with a plurality of layers and non-magnetic layers inserted to inside of the magnetic substance which forms a magnetic core are formed as one unit; coil patterns formed on either upper surfaces or lower surfaces of the plurality of layers of the magnetic substance which forms a magnetic core; and via holes formed at the plurality of layers constituting the magnetic substance which forms a magnetic core in order to electrically connect the coil patterns. A magnetic saturation is restrained by a non-magnetic layer formed in the power inductor, so that a DC bias characteristic corresponding to several hundreds of mAnull1A which could not be realized by the conventional multi-layer chip power inductor can be obtained
    • 一种芯片型功率电感器,包括:堆叠体,其形成形成堆叠有多层的磁芯的磁性体和插入到形成磁芯的磁性体的内部的非磁性层,作为一个单位; 形成在形成磁芯的磁性物质的多个层的上表面或下表面上的线圈图案; 以及形成在构成形成磁芯的磁性物质的多层的通孔,以便电连接线圈图案。 通过形成在功率电感器中的非磁性层来抑制磁饱和,从而可以获得对应于传统多层芯片功率电感器无法实现的几百mA〜1A的DC偏置特性
    • 8. 发明申请
    • Polymeric PTC device capable of returning to its initial resistance after overcurrent protection
    • 聚合PTC器件能够在过电流保护后恢复其初始电阻
    • US20030076217A1
    • 2003-04-24
    • US10045973
    • 2002-01-10
    • Ceratech Corporation
    • Kyoung-Ri ParkByoung-Su JinSang-Joon SungYu-Seok KimSeoung-Jung Ryu
    • H01C007/10
    • H01C17/06586H01C7/027
    • A polymeric positive temperature coefficient (PTC) thermistor having a particular crystalline structure to allow the resistivity of the crystalline polymer to return to its approximate original level after an overcurrent is applied thereto. Subjecting a polymer to cross-linking, heating the cross-linked polymer at a temperature of a melting point of the polymer or above the melting point of the polymer, and re-crystallizing the heated polymer forms the particular crystalline structure. By doing so, the cross-linking rate of the crystalline polymer is maximized, and the size of the crystals in the crystalline polymer is minimized. Also, the polymer layer having electrodes thereon are cut into units of a desired size before setting and/or hardening thereof, to minimize to formation of irregularities such as stress fractures, microscopic cracks, and the like.
    • 具有特定晶体结构的聚合物正温度系数(PTC)热敏电阻,以允许结晶聚合物的电阻率在施加过电流之后恢复到其近似的原始水平。 使聚合物交联,在聚合物的熔点或高于聚合物的熔点的温度下加热交联的聚合物,并重新结晶加热的聚合物形成特定的晶体结构。 通过这样做,结晶聚合物的交联速率最大化,结晶聚合物中晶体的尺寸最小化。 此外,在其固化和/或硬化之前,将具有电极的聚合物层切割成所需尺寸的单位,以最小化诸如应力断裂,微观裂纹等不规则性的形成。