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1. 发明授权

US08143100B2 Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages 有权
标题翻译：制造在堆叠封装之间具有引线接合互连的半导体多封装模块的方法
公开(公告)号：US08143100B2
公开(公告)日：2012-03-27
申请号：US11849112
申请日：2007-08-31
申请人： Marcos Karnezos
发明人： Marcos Karnezos
IPC分类号： H01L21/00
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/4334 , H01L23/49833 , H01L23/5387 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/05599 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1052 , H01L2225/1094 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/12042 , H01L2924/1433 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
摘要翻译：制造半导体多封装模块的方法包括：提供包括下基板和模具的下模制封装，将包括上基板的上模制封装固定到下封装的上表面上，并在上基板和下基板之间形成z互连。

2. 发明授权

US08030134B2 Stacked semiconductor package having adhesive/spacer structure and insulation 有权
标题翻译：堆叠的半导体封装具有粘合/间隔结构和绝缘
公开(公告)号：US08030134B2
公开(公告)日：2011-10-04
申请号：US11536424
申请日：2006-09-28
申请人： Hyeog Chan Kwon , Marcos Karnezos
发明人： Hyeog Chan Kwon , Marcos Karnezos
IPC分类号： H01L21/00
CPC分类号： H01L24/33 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/03 , H01L25/0657 , H01L2224/05554 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/49175 , H01L2224/4945 , H01L2224/73265 , H01L2224/83138 , H01L2224/8385 , H01L2224/85051 , H01L2224/85191 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.
摘要翻译：堆叠的半导体组件，其中第一裸片主动地安装在第一衬底上并且通过引线接合与衬底电互连; 在第一模具的活性侧上形成粘合剂/间隔物结构; 并且具有非导电侧的诸如管芯或封装或散热器的器件安装在粘合剂/间隔物结构上，其中不导电侧面向第一引线接合管芯。面对第一引线接合芯片的器件的侧面可以通过具有电绝缘层（例如电介质膜粘合剂）而被制成不导电的。另外，公开了制造组件的方法。

3. 发明授权

US07691681B2 Chip scale package having flip chip interconnect on die paddle 有权
标题翻译：芯片级封装，在芯片上具有倒装芯片互连
公开(公告)号：US07691681B2
公开(公告)日：2010-04-06
申请号：US12191542
申请日：2008-08-14
申请人： Cheonhee Lee
发明人： Cheonhee Lee
IPC分类号： H01L21/00
CPC分类号： H01L23/4952 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L23/49582 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/0508 , H01L2224/05567 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/136 , H01L2224/16 , H01L2224/16245 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
摘要翻译：倒装芯片引线框架封装包括管芯和具有管芯焊盘和引线的引线框架，并且在管芯的活性部位和管芯焊盘之间具有互连。此外，公开了制造包装的方法。

4. 发明授权

US07650688B2 Bonding tool for mounting semiconductor chips 有权
标题翻译：用于安装半导体芯片的接合工具
公开(公告)号：US07650688B2
公开(公告)日：2010-01-26
申请号：US10977047
申请日：2004-10-29
申请人： Hee-Bong Lee , Hyun-Joon Oh
发明人： Hee-Bong Lee , Hyun-Joon Oh
IPC分类号： B23P19/00
CPC分类号： H01L21/6838 , B23K37/047 , B23K2101/40 , Y10T29/4913 , Y10T29/49131 , Y10T29/49181 , Y10T29/53178 , Y10T29/53183 , Y10T29/53191
摘要： A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.
摘要翻译：一种真空接合工具，用于将半导体芯片拾取和接合到基板上或预先安装的模具上以形成模具堆叠，包括柄和抽吸部分。柄具有从柄的第一端延伸到第二端的真空管。柄部适于在第二端处与吸入部分协作地接合，并且柄部在第二端具有支撑抽吸部分的板。抽吸部分具有用于在拾取和放置操作期间接触半导体芯片的表面。根据本发明，抽吸部分由可弹性变形的导电或非导电材料制成。在各种实施例中，可弹性变形的吸入部分的平坦的中心区域和凹入区域的整体平坦或凹入的平坦的芯片接触表面。

5. 发明授权

US07622811B2 Semiconductor assembly with component attached on die back side 有权
标题翻译：半导体组件，其部件附着在模具背面
公开(公告)号：US07622811B2
公开(公告)日：2009-11-24
申请号：US11521974
申请日：2006-09-14
申请人： Seng Guan Chow , Francis Heap Hoe Kuan
发明人： Seng Guan Chow , Francis Heap Hoe Kuan
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49575 , H01L23/49589 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/16245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48245 , H01L2224/48247 , H01L2224/4826 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19107 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
摘要翻译：一个或多个电子部件可以安装在半导体管芯的背面。组件可以是无源组件，有源组件或其组合。这些部件可以被焊接到在管芯的背面上的信号路由，信号路由使用金属化层附接到管芯或者使用一个或多个介电层部分。将部件放置在管芯的背面可以允许组件的结合，而不必增加管芯封装的外形尺寸。

6. 发明授权

US07612444B2 Semiconductor package with flow controller 有权
标题翻译：半导体封装带流量控制器
公开(公告)号：US07612444B2
公开(公告)日：2009-11-03
申请号：US11620553
申请日：2007-01-05
申请人： Seng Guan Chow , Oh Sug Kim , Byung Tai Do
发明人： Seng Guan Chow , Oh Sug Kim , Byung Tai Do
IPC分类号： H01L23/488 , H01L23/48 , H01L21/56
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/97 , H01L2225/0651 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
摘要翻译：半导体封装可以包括附接到衬底的管芯堆叠，其中接合线电连接两者。通常，多个管芯堆叠被粘附到单个衬底上，使得可以一次制造几个半导体封装。模制复合流量控制器在一个或多个不同位置处与衬底或半导体封装最佳地相关联。流动控制器可以在封装过程中控制或引导模塑料的流动。流量控制器的尺寸，形状和位置可以平滑模制化合物的流动，从而在含有模具的基材的区域和没有模具的基材的超过区域上流动的速度基本相当。以这种方式，在封装期间可以基本上避免诸如封装，电线清扫和电线短路之类的缺陷的缺陷。

7. 发明授权

US07494847B2 Method for making a semiconductor multi-package module having inverted wire bond carrier second package 有权
标题翻译：制造具有反向引线键合载体第二封装的半导体多封装模块的方法
公开(公告)号：US07494847B2
公开(公告)日：2009-02-24
申请号：US11880893
申请日：2007-07-23
申请人： Marcos Karnezos , Flynn Carson
发明人： Marcos Karnezos , Flynn Carson
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/4334 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/48 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper wire bond carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
摘要翻译：半导体多封装模块具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中第二封装反相，其中上基板和下基板通过引线接合互连，并且其中倒置第二包装包括引线键合载体封装。另外，制造半导体多封装模块的方法通过提供包括下基板和芯片的下模塑封装，将包括反向取向的上基板的上引线键合载体封装固定在下封装的上表面上，以及在上基板和下基板之间形成z-互连。

8. 发明申请

US20080296759A1 SEMICONDUCTOR PACKAGES 有权
标题翻译：半导体封装
公开(公告)号：US20080296759A1
公开(公告)日：2008-12-04
申请号：US11757869
申请日：2007-06-04
申请人： Kambhampati Ramakrishna , Il Kwon Shim , Seng Guan Chow
发明人： Kambhampati Ramakrishna , Il Kwon Shim , Seng Guan Chow
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L24/97 , H01L25/105 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24137 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/82 , H01L2924/00
摘要： A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.
摘要翻译：半导体封装包括半导体部件（例如，管芯）和至少部分被密封剂覆盖的通孔。密封剂形成基本上平行的顶表面和底表面，其中通孔的至少一部分暴露在顶表面上。至少一个导电焊盘暴露在底表面上，并且通孔可以电耦合顶表面和底表面，以及在顶表面和底表面处连接半导体部件。附加的半导体部件可以与形成在顶表面上并耦合到通孔的电路图案耦合到顶表面。

9. 发明授权

US07420263B2 DBG system and method with adhesive layer severing 有权
标题翻译： DBG系统和粘合层切断方法
公开(公告)号：US07420263B2
公开(公告)日：2008-09-02
申请号：US11374377
申请日：2006-03-13
申请人： Seung Wook Park , Hyun Jin Park
发明人： Seung Wook Park , Hyun Jin Park
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , Y10T156/1052
摘要： An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).
摘要翻译：在晶片处理方法中，在晶片（10）的第一侧（12）中形成有凹槽（23）的阵列。后研磨带（16）粘附到第一侧。从晶片的第二侧（20）去除一定量的材料。粘合剂层（30）施加到第二侧。将切割带（24）施加到粘合剂层以形成第一晶片组件（32）。第一晶片组件被支撑在支撑表面（34）上，其中切割带面向支撑表面并且后研磨带暴露。去除后研磨带，并且通过凹槽阵列切断粘合剂层以形成单独可移除的模具（28）。

10. 发明授权

US07407080B2 Wire bond capillary tip 有权
标题翻译：导线键毛细管尖端
公开(公告)号：US07407080B2
公开(公告)日：2008-08-05
申请号：US10971202
申请日：2004-10-22
申请人： Kenny Lee , Hun-Teak Lee , Jong Kook Kim , Chulsik Kim , Ki-Youn Jang
发明人： Kenny Lee , Hun-Teak Lee , Jong Kook Kim , Chulsik Kim , Ki-Youn Jang
IPC分类号： B23K37/00
CPC分类号： B23K20/005 , B23K20/007 , B23K2101/40 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/45015 , H01L2224/45144 , H01L2224/48451 , H01L2224/78302 , H01L2224/78901 , H01L2224/85205 , H01L2924/01015 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01204 , H01L2924/01327 , H01L2924/12042 , H01L2924/20752 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A capillary tip for a wire bonding tool has a chamfer provided with at least one annular groove. The annular groove is generally oriented in a plane perpendicular to the axis of the capillary. In a sectional view through the capillary axis, the groove profile may be generally part-oval or part circular, such as semicircular or half-oval; or generally rectangular; or generally triangular. In some embodiments the width of the groove profile at the face of the chamfer is at least about one-tenth, more usually at least about one-fifth, the length of the chamfer face; and less than about one-half, more usually less than about one-third, the length of the chamfer face. In some embodiments two or more such grooves are provided. The grooved chamfer can improve the transmission of ultrasonic energy to the wire ball during formation of the bond.
摘要翻译：用于引线接合工具的毛细管尖端具有设置有至少一个环形槽的倒角。环形槽通常在垂直于毛细管轴线的平面内定向。在通过毛细管轴线的剖视图中，凹槽轮廓可以是大致为椭圆形或部分圆形的，例如半圆形或半椭圆形; 或大致矩形; 或一般为三角形。在一些实施例中，在倒角的表面处的凹槽轮廓的宽度是倒角面的长度的至少约十分之一，更通常至少约五分之一; 并且小于倒角面的长度的大约一半，更通常小于约三分之一。在一些实施例中，提供了两个或更多个这样的凹槽。沟槽倒角可以在形成接合时改善超声能量传递到丝球。

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