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    • 2. 发明授权
    • Semiconductor device for controlling switching power supply
    • 用于控制开关电源的半导体器件
    • US08084893B2
    • 2011-12-27
    • US12385527
    • 2009-04-10
    • Masanari Fujii
    • Masanari Fujii
    • H01H35/00
    • H02M1/36H02M1/32Y10T307/858
    • A semiconductor device controls a switching power supply. The semiconductor device includes a current inflow terminal; a starter circuit to cause a starting current to flow from the current inflow terminal to a power supply terminal to charge a capacitor externally connected to the power supply terminal; a control unit which controls the starter circuit to turn on to charge the capacitor with the starting current and controls the starter circuit to turn off to perform brown-out detection; a comparator which detects a brown-out state while the starter circuit is turned off; and a brown-out detection unit which receives output signals from the comparator and the control unit as inputs. The brown-out detection is performed while the starter circuit is off, so that the current inflow terminal for the starter circuit is used in common as a voltage detection terminal for detection of the brown-out state.
    • 半导体器件控制开关电源。 半导体器件包括电流流入端子; 起动电路,其使起动电流从所述电流流入端流向电源端子,对外部连接到所述电源端子的电容器进行充电; 控制单元,其控制起动器电路接通以使起动电流对电容器充电,并控制起动器电路关闭以执行欠压检测; 比较器,其在起动器电路断开时检测出欠压状态; 以及从比较器和控制单元接收输出信号作为输入的欠压检测单元。 在启动电路断开的同时执行欠压检测,使起动电路的电流流入端子作为用于检测欠压状态的电压检测端子共同使用。
    • 5. 发明授权
    • DC-DC converter and DC-DC power conversion method employing overcurrent protection
    • DC-DC转换器和采用过流保护的DC-DC电源转换方法
    • US08013585B2
    • 2011-09-06
    • US12051556
    • 2008-03-19
    • Kouhei Yamada
    • Kouhei Yamada
    • G05F1/573
    • H02M3/158H02M1/32
    • An overcurrent detection circuit (50 in FIG. 1) in a DC-DC converter is connected to a switching control circuit (1), and detects an inductor current flowing through an inductor (L) during the ON control of a switching element (Mn), so as to decide whether the inductor current has decreased down to a prescribed value. The switching control circuit (1) alters the switching timing of a control signal to extend the OFF state of a switching element (Mp) until the decrease of the inductor current to a predetermined magnitude is decided by the overcurrent detection circuit (50). Even when a delay is involved in an overcurrent detection operation, the DC-DC converter is still capable of overcurrent limitation.
    • DC-DC转换器中的过电流检测电路(图1中的50)连接到开关控制电路(1),并且在开关元件的ON控制期间检测流过电感器(L)的电感器电流(Mn ),以便确定电感器电流是否已经下降到规定值。 切换控制电路(1)改变控制信号的切换定时,以延长开关元件(Mp)的截止状态,直到由过电流检测电路(50)确定电感器电流减小至预定幅度。 即使过电流检测动作存在延迟,DC-DC转换器仍然能够进行过电流限制。
    • 6. 发明申请
    • FABRICATION METHOD FOR SEMICONDUCTOR DEVICE
    • 半导体器件制造方法
    • US20110207296A1
    • 2011-08-25
    • US13027761
    • 2011-02-15
    • Seiji Momota
    • Seiji Momota
    • H01L21/36
    • H01L29/7813H01L29/0856H01L29/66727H01L29/66734
    • A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.
    • 半导体器件制造方法包括在第一导电性的第一半导体区域的表面层上形成具有高于第一半导体区域的杂质浓度的第二半导体区域的第二导电性区域; 形成穿过所述第二半导体区域的沟槽到所述第一半导体区域; 在第二半导体区域的表面以下的高度,经由绝缘膜将第一电极嵌入沟槽内; 在所述沟槽内形成层间绝缘膜,覆盖所述第一电极; 仅在第一电极的表面上留下层间绝缘膜; 去除所述第二半导体区域使得其表面定位成低于所述第一电极和所述层间绝缘膜之间的界面; 以及通过沟槽中的绝缘膜形成与第二半导体区域接触并与第一电极相邻的第二电极。
    • 7. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • US07999317B2
    • 2011-08-16
    • US12318868
    • 2009-01-09
    • Hong-Fei LuMizushima Tomonori
    • Hong-Fei LuMizushima Tomonori
    • H01L29/66
    • H01L29/7824H01L29/086H01L29/0878H01L29/1095H01L29/42368H01L29/7394H01L29/7816
    • A p-type body region and an n-type buffer region are formed on an n− drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n− drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
    • p型体区域和n型缓冲区域形成在n漂移区域上。 在彼此接触的p型体区域上形成n ++发射极区域和p ++接触区域。 在n型缓冲区上形成p ++集电极区域。 在n漂移区域上形成绝缘膜,在n ++发射极区域,p型体区域和n漂移区域上形成栅极绝缘膜。 在绝缘膜和栅极绝缘膜上形成栅电极。 在p型体区域中形成p +低电阻率区域,并且围绕n ++发射极区域与p型体区域和p ++接触区域之间的界面。 p型体区域在体区和栅极绝缘膜之间的界面处具有两个局部最大值的杂质浓度分布。
    • 9. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20110186999A1
    • 2011-08-04
    • US12879940
    • 2010-09-10
    • Fumihiko MomoseKazumasa KidoYoshitaka NishimuraFumio Shigeta
    • Fumihiko MomoseKazumasa KidoYoshitaka NishimuraFumio Shigeta
    • H01L23/52H01L21/50
    • H01L24/80H01L21/50H01L23/52H01L2924/1305H01L2924/13055H01L2924/00
    • Hardness of bonding end portions of an external connection terminal to be bonded to circuit patterns of an insulating substrate which is not lower than 90 in Vickers hardness is disclosed. An ultrasonic welding tool is used. In the external connection terminal in which the bonding end portions are provided integrally with a bar, one of the bonding end portion located substantially in the lengthwise center of the bar is first bonded, and the other bonding end portions are bonded alternately in order toward either end. The hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased. Since the external connection terminal including the bonding end portions is bonded in such a manner that the bonding end portion located substantially in the center is first bonded and the other bonding end portions are then bonded in order of increasing distance substantially from the central bonding end portion, displacement of the bonding end portion in either end from its regular position can be suppressed to keep bonding strength high. In this manner, the bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.
    • 公开了将待接合的外部连接端子的端部与维氏硬度不低于90的绝缘基板的电路图案的接合端的硬度。 使用超声波焊接工具。 在接合端部与棒一体设置的外部连接端子中,首先将位于棒的纵向中心的接合端部中的一个接合,并且另一个接合端部交替地接合以朝向 结束。 接合端部的硬度增加,使得超声波焊接部的强度增加。 由于包括接合端部的外部连接端子以这样的方式被接合,使得基本上位于中心的接合端部被首先接合,并且接着另外的接合端部按照与中心接合端部 可以抑制任一端的接合端部从其规则位置的位移,保持接合强度高。 以这种方式,可以增加外部连接端子和绝缘基板的电路图案之间的超声波焊接部分的接合强度,从而可以确保半导体器件的长期可靠性。
    • 10. 发明申请
    • REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR
    • 反向绝缘栅双极晶体管
    • US20110186965A1
    • 2011-08-04
    • US13015229
    • 2011-01-27
    • Michio NEMOTOSouichi YOSHIDA
    • Michio NEMOTOSouichi YOSHIDA
    • H01L29/739
    • H01L29/739
    • Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.
    • 公开了其中IGBT区域和FWD区域在具有公共有源区域的半导体衬底中集成到单个体中的反向导通绝缘栅双极晶体管。 MOS栅结构在第一主表面上。 后表面侧结构位于半导体基板的第二主表面侧,并且包括与第二主表面垂直的多个凹部,其沿着第二主表面周期性重复。 在凹部之间插入有多个突出部。 后表面侧结构包括凹部的底面上的p型集电极区域,位于比集电极区域深的位置的n型第一场停止区域,突出部分的顶面上的n型阴极区域和n型第二区域 位于比阴极区域更深的位置处的突出部中的场停止区域。