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1. 发明授权

US10038088B2 Power MOSFET having improved manufacturability, low on-resistance and high breakdown voltage 有权
公开(公告)号：US10038088B2
公开(公告)日：2018-07-31
申请号：US15815391
申请日：2017-11-16
申请人： IXYS Corporation
发明人： Kyoung Wook Seok
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L29/08 , H01L23/535 , H01L29/417 , H01L23/482
CPC分类号： H01L29/7811 , H01L23/4824 , H01L23/535 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0692 , H01L29/0856 , H01L29/0878 , H01L29/1079 , H01L29/1095 , H01L29/41741 , H01L29/7813 , H05K999/99
摘要： Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.

2. 发明申请

US20180212041A1 DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT 审中-公开
公开(公告)号：US20180212041A1
公开(公告)日：2018-07-26
申请号：US15927693
申请日：2018-03-21
申请人： Silicet, LLC
发明人： Gary M. DOLNY , William R. RICHARDS, JR. , Randall MILANOWSKI
IPC分类号： H01L29/66 , H01L29/872 , H01L29/49 , H01L21/78 , H01L29/78 , H01L29/10 , H01L29/08 , H01L29/423 , H01L21/28 , H01L21/225 , H01L21/8238 , H01L21/8234 , H01L27/088 , H01L27/095
CPC分类号： H01L29/66643 , H01L21/225 , H01L21/28061 , H01L21/28123 , H01L21/7813 , H01L21/823412 , H01L21/823418 , H01L21/823814 , H01L21/823835 , H01L27/088 , H01L27/095 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42372 , H01L29/47 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/66674 , H01L29/66689 , H01L29/7806 , H01L29/7813 , H01L29/7816 , H01L29/7825 , H01L29/7835 , H01L29/7839 , H01L29/872
摘要： Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

3. 发明授权

US09837529B1 Power MOSFET having improved manufacturability, low on-resistance and high breakdown voltage 有权
公开(公告)号：US09837529B1
公开(公告)日：2017-12-05
申请号：US15284488
申请日：2016-10-03
申请人： IXYS Corporation
发明人： Kyoung Wook Seok
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L29/08 , H01L23/535 , H01L29/417
CPC分类号： H01L29/7811 , H01L23/4824 , H01L23/535 , H01L29/0623 , H01L29/0634 , H01L29/0692 , H01L29/0856 , H01L29/0878 , H01L29/1079 , H01L29/1095 , H01L29/41741 , H01L29/7813 , H05K999/99
摘要： Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.

4. 发明授权

US09419084B2 Devices, components and methods combining trench field plates with immobile electrostatic charge 有权
公开(公告)号：US09419084B2
公开(公告)日：2016-08-16
申请号：US14840744
申请日：2015-08-31
申请人： MaxPower Semiconductor Inc.
发明人： Mohamed N. Darwish , Jun Zeng
IPC分类号： H01L29/66 , H01L29/40 , H01L29/10 , H01L29/78 , H01L29/16 , H03K17/687 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0856 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/16 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/7813 , H01L29/7823 , H01L29/7827 , H01L29/7835 , H03K17/687
摘要： N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

5. 发明授权

US09337288B2 Method of manufacturing MOS-type semiconductor device 有权
标题翻译：制造MOS型半导体器件的方法
公开(公告)号：US09337288B2
公开(公告)日：2016-05-10
申请号：US14455347
申请日：2014-08-08
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shuhei Tatemichi , Takeyoshi Nishimura
IPC分类号： H01L29/423 , H01L29/10 , H01L29/08 , H01L29/66 , H01L21/02 , H01L21/265
CPC分类号： H01L29/42364 , H01L21/02238 , H01L21/02255 , H01L21/2652 , H01L21/26586 , H01L29/0856 , H01L29/1095 , H01L29/66712
摘要： A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.
摘要翻译：提供一种制造能够增加栅极氧化膜的厚度并获得高栅极耐受功率并降低开关损耗而不增加栅极阈值电压Vth的MOS型半导体器件的方法。通过使用氧化膜作为掩模，在具有n型低杂质浓度层的半导体衬底的一个主表面上选择性地形成p型阱区。随后，在p型阱区的表面上形成抗蚀剂掩模以与氧化膜掩模分离，并且从分离部选择性地形成n +型源极区。随后，除去氧化膜掩模。然后，在p型阱区的表面上形成氧化膜，除去氧化膜。随后，在半导体衬底的表面上形成涂有栅氧化膜的栅电极。

6. 发明申请

US20150380554A1 METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMED 有权
标题翻译：制造应变结构和结构的方法
公开(公告)号：US20150380554A1
公开(公告)日：2015-12-31
申请号：US14844247
申请日：2015-09-03
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Tsung-Lin LEE , Chih-Hao CHANG , Chih-Hsin KO , Feng YUAN , Jeff J. XU
IPC分类号： H01L29/78 , H01L29/08 , H01L29/66 , H01L29/165 , H01L21/31 , H01L21/311 , H01L21/02 , H01L29/06 , H01L21/306
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
摘要翻译：场效应晶体管包括包括鳍结构的衬底。场效应晶体管还包括衬底中的隔离结构。场效应晶体管还包括在衬底的顶表面下方的源/漏（S / D）凹槽。 S / D凹陷腔位于翅片结构和隔离结构之间。场效应晶体管还包括S / D凹陷腔中的应变结构。应变结构包括下部。所述下部包括第一应变层，其中所述第一应变层与所述隔离结构直接接触;以及介电层，其中所述电介质层与所述基板直接接触，并且所述第一应变层与所述第一应变层直接接触电介质层。应变结构还包括上部，其包括覆盖在第一应变层上的第二应变层。

7. 发明授权

US09147751B2 Methods of manufacturing superjunction devices 有权
标题翻译：超导装置的制造方法
公开(公告)号：US09147751B2
公开(公告)日：2015-09-29
申请号：US14580730
申请日：2014-12-23
申请人： Icemos Technology Ltd.
发明人： Samuel Anderson , Takeshi Ishiguro
IPC分类号： H01L29/74 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/66 , H01L29/78 , H01L29/417 , H01L29/06 , H01L29/10 , H01L29/08 , H01L29/73 , H01L29/737 , H01L29/739 , H01L29/861 , H01L21/265 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0856 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42364 , H01L29/42372 , H01L29/495 , H01L29/4975 , H01L29/66727 , H01L29/66734 , H01L29/7308 , H01L29/7371 , H01L29/7393 , H01L29/74 , H01L29/861
摘要： Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.
摘要翻译：提供具有端子结构的窄表面布局的超结半导体器件和制造器件的方法。端子结构的窄表面布局部分地通过在源体接触界面处将源电极连接到半导体衬底内的体接触区域而实现，所述体接触界面包括至少第一侧的身体接触区域，而不是第一半导体衬底的主表面。

8. 发明授权

US09129936B2 Devices, components and methods combining trench field plates with immobile electrostatic charge 有权
标题翻译：将沟槽场板与固定静电荷组合的器件，组件和方法
公开(公告)号：US09129936B2
公开(公告)日：2015-09-08
申请号：US13975421
申请日：2013-08-26
申请人： MaxPower Semiconductor, Inc.
发明人： Mohamed N. Darwish , Jun Zeng
IPC分类号： H01L29/66 , H01L29/40 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0856 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/16 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/7813 , H01L29/7823 , H01L29/7827 , H01L29/7835 , H03K17/687
摘要： N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
摘要翻译：其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。

9. 发明申请

US20140027858A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140027858A1
公开(公告)日：2014-01-30
申请号：US14047720
申请日：2013-10-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mitsuhiko KITAGAWA
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L29/0634 , H01L29/0856 , H01L29/0878 , H01L29/4236 , H01L29/7391 , H01L29/7394 , H01L29/7397 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7831 , H01L29/7838
摘要： A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
摘要翻译：半导体器件包括：具有第一端部和第二端部的半导体层; 第一主电极，设置在第一端部上并与半导体层电连接; 第二主电极，设置在第二端部并与半导体层电连接; 第一栅电极，其经由第一栅极绝缘膜设置在由所述第一端部朝向所述第二端部形成的多个第一沟槽中; 以及第二栅电极，其经由第二栅极绝缘膜设置在由所述第二端部朝向所述第一端部形成的多个第二沟槽中。多个第一栅电极之间的间隔和多个第二栅电极之间的间隔为200nm以下。

10. 发明申请

US20130334597A1 POWER SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20130334597A1
公开(公告)日：2013-12-19
申请号：US13720344
申请日：2012-12-19
申请人： Hiroaki Yamashita , Masaru Izumisawa , Syotaro Ono , Hiroshi Ohta
发明人： Hiroaki Yamashita , Masaru Izumisawa , Syotaro Ono , Hiroshi Ohta
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1033 , H01L29/1095 , H01L29/4236 , H01L29/42376 , H01L29/66333 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7802
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region.

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