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1. 发明申请

US20110051934A1 DATA RECEIVING DEVICE, DATA RECEIVING METHOD AND PROGRAM 审中-公开
标题翻译：数据接收设备，数据接收方法和程序
公开(公告)号：US20110051934A1
公开(公告)日：2011-03-03
申请号：US12823768
申请日：2010-06-25
申请人： Motoshige IKEDA
发明人： Motoshige IKEDA
IPC分类号： H04K1/00
CPC分类号： H04L25/05 , H04L7/0029 , H04L25/03866
摘要： A data receiving device includes an elastic buffer which receives data as receiving data and adjusts timing with a sender, the data being scrambled and sent from the sender, an interpolation circuit which performs predetermined interpolation processing on the data subjected to timing adjustment by the elastic buffer to output the data, and a descramble circuit which descrambles the data output from the interpolation circuit. The receiving data includes data set for adjusting timing. The data set is for adjusting timing with the sender. The interpolation circuit replaces existing data with data for adjusting timing and outputs the data for adjusting timing as required after first receiving normal data for adjusting timing so that a desired number of data for adjusting timing is included in the data set for adjusting timing.
摘要翻译：数据接收装置包括：弹性缓冲器，其接收数据作为接收数据，并且利用发送器调整定时，数据被加扰并从发送器发送;内插电路，对由弹性缓冲器进行定时调整的数据执行预定的插值处理输出数据，以及解扰电路，对从内插电路输出的数据进行解扰。接收数据包括用于调整定时的数据集。数据集用于调整发送方的时间。内插电路用现有数据替换用于调整定时的数据，并且在首先接收用于调整定时的正常数据之后根据需要输出用于调整定时的数据，使得用于调整定时的所需数量的用于调整定时的数据被包括在用于调整定时的数据组中。

2. 发明申请

US20110050983A1 Apparatus, method, and program product for autofocus 有权
标题翻译：用于自动对焦的装置，方法和程序产品
公开(公告)号：US20110050983A1
公开(公告)日：2011-03-03
申请号：US12801653
申请日：2010-06-18
申请人： Hiromi Takeda , Takeshi Ohtsuki
发明人： Hiromi Takeda , Takeshi Ohtsuki
IPC分类号： H04N5/232 , G03B13/36
CPC分类号： G03B13/36 , G02B7/08 , G02B7/36 , H04N5/23212
摘要： An exemplary embodiment of the present invention is an autofocus method that includes moving a focus lens according to an image signal generated from an image of a subject formed by an imaging optical system with a focus lens, obtaining a focus contrast of each of multiple image signals generated in a case of moving a position of the focus lens; and determining a moving direction of the focus lens according to the multiple obtained focus contrasts in response to a focus instruction.
摘要翻译：本发明的示例性实施例是一种自动聚焦方法，其包括根据由具有聚焦透镜的成像光学系统形成的被摄体的图像生成的图像信号移动聚焦透镜，获得多个图像信号中的每一个的聚焦对比度在移动聚焦透镜的位置的情况下产生; 以及响应于聚焦指令，根据所获得的多个焦点对比度确定所述聚焦透镜的移动方向。

3. 发明申请

US20110050761A1 PIXEL CIRCUIT AND DISPLAY DEVICE 审中-公开
标题翻译：像素电路和显示设备
公开(公告)号：US20110050761A1
公开(公告)日：2011-03-03
申请号：US12839831
申请日：2010-07-20
申请人： Teru YONEYAMA
发明人： Teru YONEYAMA
IPC分类号： G09G5/02
CPC分类号： G09G3/325 , G09G3/2081 , G09G2310/0259 , G09G2310/0262 , G09G2320/0223
摘要： A display device uses a plurality of pixel circuits each of which includes a light-emitting element; a light-emission control switching element; a current control circuit for supplying a driving current, which corresponds to gray-level display data, to the light-emitting element via the light-emission control switching element; and a voltage control circuit, which includes a first capacitance element for storing a voltage corresponding to the gray-level display data, and controls ON/OFF operation of the light-emission switching element in accordance with the voltage stored. If the gray-level display data is data for causing the light-emitting element to display less than a certain luminance, the current control circuit supplies the light-emitting element with a constant driving current corresponding to the gray-level display data for displaying the certain luminance, and the voltage control circuit controls the ON time of the light-emission control switching element in accordance with a voltage stored.
摘要翻译：显示装置使用多个像素电路，每个像素电路包括发光元件; 发光控制开关元件; 电流控制电路，用于经由发光控制开关元件向发光元件提供对应于灰度级显示数据的驱动电流; 以及电压控制电路，其包括用于存储与灰度级显示数据相对应的电压的第一电容元件，并且根据存储的电压来控制发光开关元件的接通/断开操作。如果灰度级显示数据是用于使发光元件显示小于一定亮度的数据，则电流控制电路向与发送元件的灰度级显示数据相对应的恒定驱动电流供给发光元件，一定的亮度，并且电压控制电路根据存储的电压来控制发光控制开关元件的接通时间。

4. 发明申请

US20110050197A1 Reference current or voltage generation circuit 审中-公开
标题翻译：参考电流或电压发生电路
公开(公告)号：US20110050197A1
公开(公告)日：2011-03-03
申请号：US12805239
申请日：2010-07-20
申请人： Tachio Yuasa
发明人： Tachio Yuasa
IPC分类号： G05F3/16
CPC分类号： G05F3/242
摘要： A reference current or voltage generation circuit which forms a self feedback circuit with a plurality of transistors and generates a reference current or a reference voltage, the reference current or voltage generation circuit including a normally-on type transistor that has a gate connected to a first power supply and is connected between a node and a second power supply. Moreover, a voltage of the node is substantially equal to a voltage of the first power supply when the reference current or voltage generation circuit does not operate, and the voltage of the node fluctuates from the voltage of the first power supply toward a voltage of the second power supply by a predetermined value or more when the reference current or voltage generation circuit operates.
摘要翻译：一种参考电流或电压产生电路，其形成具有多个晶体管的自反馈电路并产生参考电流或参考电压，所述参考电流或电压产生电路包括常栅型晶体管，其具有连接到第一电源并连接在节点和第二电源之间。此外，当基准电流或电压产生电路不工作时，节点的电压基本上等于第一电源的电压，并且节点的电压从第一电源的电压朝向当基准电流或电压产生电路工作时，第二电源达预定值或更多。

5. 发明申请

US20110043295A1 Semiconductor device having an ESD protection circuit 有权
标题翻译：具有ESD保护电路的半导体器件
公开(公告)号：US20110043295A1
公开(公告)日：2011-02-24
申请号：US12926177
申请日：2010-10-29
申请人： Masakazu Ikegami
发明人： Masakazu Ikegami
IPC分类号： H03B5/32 , H02H9/00 , H03F3/45
CPC分类号： H03K19/00361 , H01L27/0266
摘要： A semiconductor integrated circuit, includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, a first transistor which has a source-drain route connected between an external terminal and a first voltage, and a gate terminal connected to the output terminal of the operational amplifier; and a second transistor which has a source-drain route connected between the first input terminal of the operational amplifier and the first voltage, and a gate terminal connected to the output terminal of the operational amplifier.
摘要翻译：一种半导体集成电路，包括：运算放大器，包括第一输入端子，第二输入端子和输出端子;第一晶体管，其具有连接在外部端子和第一电压之间的源极 - 漏极连接;以及栅极端子连接到运算放大器的输出端; 以及第二晶体管，其具有连接在运算放大器的第一输入端和第一电压之间的源极 - 漏极通路，以及连接到运算放大器的输出端的栅极端子。

6. 发明申请

US20110039396A1 Semiconductor device and method of fabricating semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US20110039396A1
公开(公告)日：2011-02-17
申请号：US12923982
申请日：2010-10-19
申请人： Kousaku Uoya
发明人： Kousaku Uoya
IPC分类号： H01L21/302
CPC分类号： H01L23/3114 , H01L21/6835 , H01L21/6836 , H01L23/3157 , H01L23/3185 , H01L24/12 , H01L24/27 , H01L2221/68327 , H01L2221/68377 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05147 , H01L2224/05166 , H01L2224/16 , H01L2224/274 , H01L2924/01029 , H01L2924/10253 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： A method of fabricating a semiconductor device from a semiconductor wafer, having external connecting terminals on one side of the semiconductor wafer and a cover layer on another side of the semiconductor wafer, includes forming a groove with a first width from the one side to at least an interface between the semiconductor wafer and the cover layer in the semiconductor wafer, and cutting the cover layer with a second width from a bottom side of the groove. The second width is narrower than the first width.
摘要翻译：一种从半导体晶片制造半导体器件的方法，在半导体晶片的一侧具有外部连接端子和在半导体晶片的另一侧上的覆盖层，包括从一侧到至少形成具有第一宽度的沟槽在半导体晶片中的半导体晶片和覆盖层之间的界面，并且从凹槽的底侧以第二宽度切割覆盖层。第二宽度比第一宽度窄。

7. 发明申请

US20110033982A1 Lead-forming die and method of manufacturing semiconductor device utilizing lead-forming die 审中-公开
标题翻译：铅成形模以及使用铅成形模的半导体器件的制造方法
公开(公告)号：US20110033982A1
公开(公告)日：2011-02-10
申请号：US12805368
申请日：2010-07-27
申请人： Takeshi Kimura
发明人： Takeshi Kimura
IPC分类号： H01L21/60 , H01L21/48
CPC分类号： H01L21/4842 , H01L23/49555 , H01L2924/0002 , H01L2924/00
摘要： Provided is that a lead-forming die includes an upper die and a lower die disposed so as to oppose the upper die; a supporting unit for semiconductor package, provided on an upper face of the lower die; a moving unit provided on a lower face of the upper die and movable in a direction that the upper die and the lower die oppose each other; a plurality of shafts supported by the moving unit so as to axially move with respect thereto; a presser provided above the supporting unit for semiconductor package, and at a lower end portion of the shaft; and a locking device that stops a movement of the shaft, provided between the upper die and the moving unit.
摘要翻译：提供一种铅成形模包括上模和下模，以与上模相对设置; 半导体封装的支撑单元，设置在下模的上表面上; 设置在上模的下表面上并可沿上模和下模彼此相对的方向移动的移动单元; 由所述移动单元支撑以便相对于其轴向移动的多个轴; 设置在所述用于半导体封装的支撑单元上方的压脚以及所述轴的下端部; 以及设置在上模和移动单元之间的止动轴的移动的锁定装置。

8. 发明申请

US20110032135A1 D/A CONVERTER 审中-公开
标题翻译： D / A转换器
公开(公告)号：US20110032135A1
公开(公告)日：2011-02-10
申请号：US12827471
申请日：2010-06-30
申请人： Fumio Tonomura
发明人： Fumio Tonomura
IPC分类号： H03M1/76
CPC分类号： H03M1/68 , H03M1/76
摘要： A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage.
摘要翻译： DA转换器包括：电阻串，其产生包括上限电压，下限电压和中间电压的多个电压;第一选择器，根据较低位选择并输出多个电压中的第一电压; 所述第一电压从所述中间电压和低于所述中间电压的电压中选择;第二选择器，其根据较高位选择和输出第二电压，所述第二电压是较低电源电压和所述中间电压之一，高于中间电压的电压;第三选择器，根据较高位选择和输出第三电压，第三电压选自下限电压和较低电源电压; 以及放大器，其添加第一电压和第二电压并减去第三电压。

9. 发明申请

US20110032031A1 AMPLIFIER CIRCUIT AND LIGHT RECEIVING AMPLIFIER CIRCUIT USING THE SAME 失效
标题翻译：放大器电路和使用相同的接收放大器的电路
公开(公告)号：US20110032031A1
公开(公告)日：2011-02-10
申请号：US12813997
申请日：2010-06-11
申请人： Tadashi JAHANA
发明人： Tadashi JAHANA
IPC分类号： H03F1/34
CPC分类号： H03F3/087 , H03F1/34 , H03F3/45475 , H03F2203/45136 , H03F2203/45511 , H03F2203/45512 , H03F2203/45514 , H03F2203/45526 , H03F2203/45528
摘要： An amplifier circuit includes an amplifier unit that amplifies a signal received by an input terminal and outputs the amplified signal to an output terminal, a feedback capacitor that is connected between the input terminal of the amplifier and the output terminal, and a controller that varies a capacitance in the feedback capacitor for a certain period when a potential of the output terminal in the amplifier unit becomes higher or lower than a certain potential.
摘要翻译：放大器电路包括：放大单元，放大由输入端接收的信号，并将放大后的信号输出到输出端;反馈电容，连接在放大器的输入端与输出端;以及控制器，当放大器单元中的输出端子的电位变得高于或低于某一电位时，反馈电容器中的电容一定时间。

10. 发明申请

US20110032014A1 Delay locked loop circuit and signal delay method 审中-公开
标题翻译：延迟锁相环电路和信号延时方式
公开(公告)号：US20110032014A1
公开(公告)日：2011-02-10
申请号：US12801894
申请日：2010-06-30
申请人： Masahiko Shihara , Atsushi Tangoda
发明人： Masahiko Shihara , Atsushi Tangoda
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0816
摘要： A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.
摘要翻译：乘法器PLL将参考时钟相乘并输出相乘的时钟。 DLL将乘法器PLL的时钟输出与通过延迟乘法器PLL的时钟输出获得的时钟进行比较。该DLL根据比较结果产生具有给定量的延迟的延迟信号。延迟控制信号运算电路基于由DLL生成的延迟信号生成延迟控制信号。第一延迟电路基于由延迟控制信号操作电路产生的延迟控制信号延迟输入信号。

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