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1. 发明授权

US09659636B2 NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations 有权
公开(公告)号：US09659636B2
公开(公告)日：2017-05-23
申请号：US14806629
申请日：2015-07-22
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C16/04 , G11C11/56 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/34 , G11C7/14 , G11C7/18 , G11C29/50
CPC分类号： G11C11/5635 , G11C7/14 , G11C7/18 , G11C11/56 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C2029/5002
摘要： A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.

2. 发明授权

US09530492B2 NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations 有权
标题翻译：用于多WL和全BL同时擦除，擦除验证，程序，程序验证和读取操作的NAND阵列高性能BL结构
公开(公告)号：US09530492B2
公开(公告)日：2016-12-27
申请号：US14953384
申请日：2015-11-29
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/06 , G11C16/14 , G11C16/24
CPC分类号： G11C11/5635 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5641
摘要： Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.
摘要翻译：提供了一些具有1级或2级破碎的BL级别结构的2D和3D HiNAND闪存阵列，用于分散块中的Multiple Whole-WL和All-BL同时操作。全局位线（GBL）被划分为多个1（顶）级破碎金属2 GBL加上可选的较低级别的破碎金属1局部位线（LBL）。可以通过水平金属电源线LBL选择性地提供高于Vdd的优选Vinhibit电源，以对所选择的破坏的GBL / LBL充电，也可以经由串源线选择性地放电。用于NAND电池数据传感的破碎GBL / LBL电容器的充电和放电的电荷共享技术用于读取和验证操作，具有降低的功耗和延迟。用于恢复存储在破碎的GBL / LBL电容器中的所需程序数据的恢复技术用于多WL和全BL程序和程序验证操作，具有减少的程序电流，用于最高程序产生优异的P / E周期。

3. 发明授权

US09595319B2 Partial/full array/block erase for 2D/3D hierarchical NAND 有权
标题翻译： 2D / 3D分层NAND的部分/全阵列/块擦除
公开(公告)号：US09595319B2
公开(公告)日：2017-03-14
申请号：US15137284
申请日：2016-04-25
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C11/56 , G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3445 , H01L27/11556 , H01L27/11582
摘要： A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.
摘要翻译：一种新颖的2D / 3D分层BL NAND阵列，其独立的基板上具有至少一个平面，包括分别与多个局部位线（LBL）相关联的多个LG组，所述多个局部位线布置在低于多个破碎或非断开全局连接到页面缓冲区的位线（GBL）。每个LG组包括多个块，并且将独立电源线连接到多个LBL中的每一个。每个块包括N位2D / 3D NAND串，每个NAND串都具有串联连接的S个单元，并由两个串选择器件终止并耦合到公共源极线。特别地，随机大小的部分块WL从2D / 3D NAND阵列的一个平面的随机选择的LG组的每个块中选择同时进行擦除，边界WL可选地被预读，并且编程到2D的另一个平面 / 3D NAND阵列或可选地保存在片外，并回写数据安全。

4. 发明授权

US09524773B2 Multi-task concurrent/pipeline NAND operations on all planes 有权
公开(公告)号：US09524773B2
公开(公告)日：2016-12-20
申请号：US14966894
申请日：2015-12-11
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C11/56 , G11C16/34 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C7/10 , H01L27/115
CPC分类号： G11C11/5635 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3445 , G11C16/3459 , H01L27/1157 , H01L27/11582
摘要： This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

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