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1. 发明申请

US20160099047A1 MULTI-TASK CONCURRENT/PIPELINE NAND OPERATIONS ON ALL PLANES 审中-公开
公开(公告)号：US20160099047A1
公开(公告)日：2016-04-07
申请号：US14966894
申请日：2015-12-11
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5635 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3445 , G11C16/3459 , H01L27/1157 , H01L27/11582
摘要： This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

2. 发明申请

US20150071007A1 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN 有权
标题翻译： 1T1b和2T2b基于闪存，面向数据的EEPROM设计
公开(公告)号：US20150071007A1
公开(公告)日：2015-03-12
申请号：US14546294
申请日：2014-11-18
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/14 , G11C16/26 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0425 , G11C16/0458 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2216/14
摘要： An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.
摘要翻译：提供了一个单晶体管一位（1T1b）基于闪存的EEPROM单元，以及改进的键操作方案，包括施加负字线电压和降低的位线电压用于执行擦除操作，这大大降低了高压应力每个单元用于增强编程/擦除周期，同时减小单元大小。由1T1b闪存的EEPROM单元制成的阵列可以在每个程序周期的半页或全页分割编程和预充电周期下进行操作。在单元阵列中利用由Vdd器件制成的PGM缓冲器进一步节省了硅面积。另外，公开了从1T1b单元得到的双晶体管二位二位（2T2b）EEPROM单元，其额外的单元尺寸减小，但是编程和擦除操作与1T1b单元的操作相同，有利于没有过程变化，大大增强了存储密度，卓越的程序/擦除耐久循环，以及在高温环境下运行的能力。

3. 发明申请

US20140050025A1 LOW-VOLTAGE FAST-WRITE PMOS NVSRAM CELL 有权
标题翻译：低电压快速写入PMOS NVSRAM单元
公开(公告)号：US20140050025A1
公开(公告)日：2014-02-20
申请号：US13965031
申请日：2013-08-12
申请人： Hsing-Ya Tsao , Peter Wung Lee
发明人： Hsing-Ya Tsao , Peter Wung Lee
IPC分类号： G11C14/00
CPC分类号： G11C14/0063 , G11C14/00 , G11C16/04 , G11C16/0433 , G11C16/16
摘要： This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.
摘要翻译：本发明公开了一种低电压快写12T或14T PMOS NVSRAM单元结构，其包括6T LV SRAM单元和一对两个3T或4T HV PMOS闪存串。由于PMOS和NMOS闪存单元的反向阈值电压分辨率，该PMOS NVSRAM单元在数据写入操作期间具有超过NMOS NVSRAM单元在SRAM和闪存对之间具有相同数据极性的优势。此外，该PMOS NVSRAM的PMOS闪存单元使用与NMOS NVSRAM类似的低电流FN隧穿方案，因此快速数据编程和擦除可以同时实现高达100 Mb的大密度。因此，在上电期间闪存数据加载到SRAM单元期间，具有1.2V VDD的NVSRAM的低功耗电压操作可以轻松设计，无需将FSL线耦合到任何VDD电平。

4. 发明授权

US08634254B2 Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction 失效
标题翻译：具有不同栅极氧化物厚度的单晶硅电可擦除可编程存储器件，使用PIP或MIM耦合电容器进行电池尺寸减小以及同时使用VPP和VNN进行写电压降低
公开(公告)号：US08634254B2
公开(公告)日：2014-01-21
申请号：US13052049
申请日：2011-03-19
申请人： Fu-Chang Hsu , Peter Wung Lee
发明人： Fu-Chang Hsu , Peter Wung Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/06
摘要： A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first plate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.
摘要翻译：单个多晶硅浮栅非易失性存储器件具有存储MOS晶体管和至少一个多晶绝缘体 - 多晶（PIP）或金属 - 绝缘体 - 金属（MIM）电容器，其制造尺寸可以使用当前的低电压逻辑集成电路处理。 PIP或MIM电容器是耦合电容器，其中第一板连接到存储MOS晶体管的浮置栅极，以形成浮动栅极节点。耦合PIP或MIM电容将施加到PIP或MIM电容器的第二板的电压电平耦合到具有大约90％的大耦合比的浮动栅极节点，以便启动用于擦除或编程存储器件的Fowler-Nordheim隧道效应。存储器件还可以具有另一个PIP或MIM电容器，其中第一板连接到用作隧道电容器的存储MOS晶体管的浮置栅极。

5. 发明授权

US08531885B2 NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers 失效
标题翻译：基于NAND的2T2b NOR闪存阵列，使用二极管连接到电池的源节点，使用最少数量的金属层进行尺寸减小
公开(公告)号：US08531885B2
公开(公告)日：2013-09-10
申请号：US13116002
申请日：2011-05-26
申请人： Fu-Chang Hsu , Peter Wung Lee
发明人： Fu-Chang Hsu , Peter Wung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0483 , H01L27/1021 , H01L27/11524 , H01L29/872
摘要： A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.
摘要翻译：基于NAND的NOR闪存阵列具有以行和列排列的基于NAND的NOR闪存单元的矩阵。列中每两个相邻的基于NAND的NOR闪存单元共享通过二极管连接到公共源极线的公共源节点。源极线可以由金属层制成并且与源节点直接接触或通过欧姆接触形成肖特基势垒二极管。源极线还可以由多晶硅或金属层制成并且通过柱结构的多晶硅二极管和导电层连接到源节点。二极管也可以通过在源节点的重N +掺杂区域中封装P / N +结二极管而形成在源节点中。

6. 发明申请

US20130215683A1 Three-Dimensional Flash-Based Combo Memory and Logic Design 审中-公开
标题翻译：三维闪存组合存储器和逻辑设计
公开(公告)号：US20130215683A1
公开(公告)日：2013-08-22
申请号：US13586451
申请日：2012-08-15
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/04 , H01L27/088
CPC分类号： G11C16/0466 , G11C11/5671 , H01L27/088 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/7926
摘要： A three-dimensional NAND-based NOR nonvolatile memory cell has two three-dimensional SONOS-type charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The first charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the second charge retaining transistor's source is connected to a source line and is parallel to the bit line. The three-dimensional NAND-based NOR nonvolatile memory cell may be reconfigured to function as a PLD cell, an FPGA switching cell, and an EEPROM cell
摘要翻译：三维基于NAND的非易失性存储单元具有串联串联布置的两个三维SONOS型电荷保持晶体管，使得一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过电荷当不选择电荷保持晶体管来确定三维基于NAND的非易失性存储单元的数据状态时，获得晶体管。第一电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且第二电荷保持晶体管的源极连接到源极线并且平行于位线。可以将基于三维NAND的NOR非易失性存储单元重新配置为用作PLD单元，FPGA开关单元和EEPROM单元

7. 发明授权

US08472251B2 Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device 失效
标题翻译：单晶硅电可擦除和可编程非易失性存储器件
公开(公告)号：US08472251B2
公开(公告)日：2013-06-25
申请号：US12378036
申请日：2009-02-10
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C16/04 , G11C11/34 , H01L29/788 , H01L29/66
CPC分类号： H01L29/7883 , G11C16/0441 , G11C2216/10 , H01L27/11558 , H01L29/42324
摘要： A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.
摘要翻译：单个多晶硅浮动非易失性存储单元具有MOS电容器和存储MOS晶体管，其制造尺寸允许使用电流低电压逻辑集成电路工艺制造。 MOS电容器具有连接到存储MOS晶体管的栅极的第一板，以形成浮栅节点。与存储MOS晶体管的物理尺寸相比，MOS电容器的物理尺寸相对较大（大约10倍），以在MOS电容器的第二板和浮置电容器之间建立大的耦合比（大于80％）门节点。当向MOS电容器的第二板施加电压，并且施加到MOS晶体管的源极区域或漏极区域的电压在MOS晶体管的栅极氧化物内建立电压场，从而启动Fowler-Nordheim边缘隧道。

8. 发明申请

US20120063233A1 EEPROM-based, data-oriented combo NVM design 有权
公开(公告)号：US20120063233A1
公开(公告)日：2012-03-15
申请号：US13200010
申请日：2011-09-15
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C16/10 , H01L21/336
CPC分类号： H01L21/28273 , G11C16/0441 , G11C16/0483 , G11C16/10 , H01L27/11521 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

9. 发明申请

US20110235437A1 Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction 失效
标题翻译：使用PIP或MIM耦合电容器进行单元尺寸减小的单多晶硅电可擦除可编程存储器件，并且用于写电压降低的同时VPP和VNN
公开(公告)号：US20110235437A1
公开(公告)日：2011-09-29
申请号：US13052049
申请日：2011-03-19
申请人： Fu-Chang Hsu , Peter Wung Lee
发明人： Fu-Chang Hsu , Peter Wung Lee
IPC分类号： G11C16/14 , G11C16/02
CPC分类号： G11C16/0466 , G11C16/06
摘要： A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first pate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.
摘要翻译：单个多晶硅浮栅非易失性存储器件具有存储MOS晶体管和至少一个多晶绝缘体 - 多晶（PIP）或金属 - 绝缘体 - 金属（MIM）电容器，其制造尺寸可以使用当前的低电压逻辑集成电路处理。 PIP或MIM电容器是耦合电容器，其中第一板连接到存储MOS晶体管的浮置栅极，以形成浮动栅极节点。耦合PIP或MIM电容将施加到PIP或MIM电容器的第二板的电压电平耦合到具有大约90％的大耦合比的浮动栅极节点，以便启动用于擦除或编程存储器件的Fowler-Nordheim隧道效应。存储器件还可以具有另一个PIP或MIM电容器，其中第一头连接到存储MOS晶体管的浮置栅极用作隧道电容器。

10. 发明申请

US20100329011A1 MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE 失效
标题翻译：具有基于NAND的NAND和NAND闪存的存储器系统和集成在一个芯片中的SRAM用于混合数据，代码和缓存存储
公开(公告)号：US20100329011A1
公开(公告)日：2010-12-30
申请号：US12701509
申请日：2010-02-05
申请人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C7/1075 , G11C8/16
摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.
摘要翻译：存储器系统包括NAND闪存，NOR闪存和在单个芯片上制造的SRAM。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。地址总线是双向的，用于接收代码，数据和地址以及发送输出。数据总线也是双向的，用于接收和发送数据。一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

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