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1. 发明申请

US20220108059A1 Optimizing Place-and-Routing Using a Random Normalized Polish Expression 有权
公开(公告)号：US20220108059A1
公开(公告)日：2022-04-07
申请号：US17644320
申请日：2021-12-14
申请人： Pulsic Limited
发明人： Mark Waller , Paul Clewes , Liang Gao , Jonathan Longrigg
IPC分类号： G06F30/392 , G06F30/39 , G06F30/394
摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

2. 发明授权

US11281828B1 Automated analog layout 有权
公开(公告)号：US11281828B1
公开(公告)日：2022-03-22
申请号：US17028937
申请日：2020-09-22
申请人： Pulsic Limited
发明人： Paul Clewes , Liang Gao , Jonathan Longrigg
IPC分类号： G06F30/327 , G06F30/394 , G06F30/392 , G06F111/12
摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

3. 发明授权

US11030374B1 Filling vacant areas of an integrated circuit design 有权
公开(公告)号：US11030374B1
公开(公告)日：2021-06-08
申请号：US16909997
申请日：2020-06-23
申请人： Pulsic Limited
发明人： Graham Balsdon
IPC分类号： G06F30/30 , G06F30/392 , G06F30/39 , G06F119/18
摘要： Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

4. 发明授权

US09245082B2 High-speed shape-based router 有权
标题翻译：高速形状路由器
公开(公告)号：US09245082B2
公开(公告)日：2016-01-26
申请号：US11425504
申请日：2006-06-21
申请人： Jeremy Birch
发明人： Jeremy Birch
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , Y02A10/46
摘要： A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.
摘要翻译：基于高速形状的路由器适用于标准单元数字设计，芯片级块装配设计和其他设计风格。在本发明的流程中，该技术为要路由的每个网络建立初始结构。网或其中的一部分被订购。网络的每个部分可以使用脊线路由搜索，深度优先搜索或空间洪泛搜索或这些的任何组合来路由。在哪些部分出现故障或发生错误的情况下，会发现冲突，并且技术再次尝试路由。

5. 发明授权

US08966425B1 Clock tree generation and routing 有权
标题翻译：时钟树生成和路由
公开(公告)号：US08966425B1
公开(公告)日：2015-02-24
申请号：US13829512
申请日：2013-03-14
申请人： Pulsic Limited
发明人： Robert Eisenstadt , Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.
摘要翻译：一种技术使用基于脊柱的架构（使用脊柱路由），同时也使用集群放置来生成小规模时钟树。技术用于控制时钟汇聚簇内容，以最小化时钟偏移，最小化时钟缓冲区计数，并最大限度地减少路由资源的使用。这种方式还为用户提供了足够的结构和控制来定制小型高效时钟树，并且还可以降低时钟功耗。

6. 发明授权

US08332805B1 Automatically routing nets according to parasitic constraint rules 有权
标题翻译：根据寄生约束规则自动布线网络
公开(公告)号：US08332805B1
公开(公告)日：2012-12-11
申请号：US13180256
申请日：2011-07-11
申请人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
发明人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.
摘要翻译：一种自动布线集成电路设计互连的系统，同时考虑到它所产生的布线的寄生问题。该系统将能够选择合适的布线图案，使信号满足其性能要求。

7. 发明授权

US08099700B1 Automatic integrated circuit routing using spines 有权
标题翻译：使用脊柱自动集成电路布线
公开(公告)号：US08099700B1
公开(公告)日：2012-01-17
申请号：US11838726
申请日：2007-08-14
申请人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
发明人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
摘要翻译：提供提供改进的路由质量的集成电路的互连路由的方法和技术。在本发明的一个实施例中，该技术提供线性脊柱互连路由。在诸如DRAM和SRAM存储器设计的存储器阵列块中，连接的引脚通常在第一方向上分开大距离，在第二方向或脊柱或通道区域上分开小距离。在脊椎区域内定义路线区域。在一个实施例中，识别路线区域中的障碍物并且划定对应的禁止区域。线性脊线互连在路线区域内沿第一方向路由，同时避免禁止区域。引脚通过缝合互连连接到脊柱互连。缝合互连通常沿第二方向布线。

8. 发明授权

US08095903B2 Automatically routing nets with variable spacing 有权
标题翻译：自动路由具有可变间距的网络
公开(公告)号：US08095903B2
公开(公告)日：2012-01-10
申请号：US11555202
申请日：2006-10-31
申请人： Jeremy Birch , Mark Waller , Graham Balsdon
发明人： Jeremy Birch , Mark Waller , Graham Balsdon
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.
摘要翻译：一种技术将自动路由集成电路的互连，并调整磁道或互连之间的间距，以提高性能或减少电迁移效应。通过增加某些轨道或移动轨道之间的间距，性能可以提高，因为轨道将在相同层或不同层上的附近轨道具有更高的抗噪声能力。自动路由器将根据一个或多个因素来调整轨道之间的间距。这些因素可以包括与轨道相关的电流，轨道的宽度，电容，电感和电迁移。在具体实现中，该技术使用基于形状的方法，其中不使用网格。该技术可以进一步改变轨道的宽度。

9. 发明授权

US10783292B1 Automated analog layout 有权
公开(公告)号：US10783292B1
公开(公告)日：2020-09-22
申请号：US15162458
申请日：2016-05-23
申请人： Pulsic Limited
发明人： Paul Clewes , Liang Gao , Jonathan Longrigg
IPC分类号： G06F17/50 , G06F30/327 , G06F30/392 , G06F30/394 , G06F111/12
摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

10. 发明授权

US10769343B2 High-speed shape-based router 有权
公开(公告)号：US10769343B2
公开(公告)日：2020-09-08
申请号：US16506970
申请日：2019-07-09
申请人： Pulsic Limited
发明人： Jeremy Birch
IPC分类号： G06F30/394
摘要： A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

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