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1. 发明授权

US08249161B2 Video decoder incorporating reverse variable length decoding 有权
标题翻译：视频解码器结合反向可变长度解码
公开(公告)号：US08249161B2
公开(公告)日：2012-08-21
申请号：US11536555
申请日：2006-09-28
申请人： Mahesh Narain Shukla , Dipti Rani Taur
发明人： Mahesh Narain Shukla , Dipti Rani Taur
IPC分类号： H04N11/02 , H04N7/12
CPC分类号： H04N19/69 , H04N19/426 , H04N19/44 , H04N19/61 , H04N19/895 , H04N19/91
摘要： A video decoder receiving an encoded bit stream includes a header decoder which receives the encoded bit stream, a variable length decoder connected to the header decoder which receives the header decoded data, a quantizer and compensator connected to the variable length decoder, for, during backward decoding, performing inverse quantization, transformation and motion compensation of the variable length decoded data. The inverse quantization, transformation and motion compensation of the header decoded data is done consecutively to provide complete decoded data till a first point in the backward direction such that the first point is either the error point or a point before the end point of the macroblock containing error detected in the forward direction and the output buffer is connected to the quantizer and compensator for storing complete decoded data, thereby eliminating the use of intermediate buffer for storing variable length decoded data during backward decoding and reducing the number of computations.
摘要翻译：接收编码比特流的视频解码器包括接收编码比特流的头解码器，连接到接收头解码数据的头解码器的可变长度解码器，连接到可变长度解码器的量化器和补偿器，用于在后向解码，执行逆量化，可变长度解码数据的变换和运动补偿。标题解码数据的逆量化，变换和运动补偿是连续完成的，以提供完整的解码数据，直到向后方向上的第一点，使得第一点是错误点或包含宏块的结束点之前的点在正向检测到的错误和输出缓冲器连接到量化器和补偿器，用于存储完整的解码数据，从而在反向解码期间消除了用于存储可变长度解码数据的中间缓冲器的使用，并减少了计算次数。

2. 发明授权

US08830098B2 Sigma-delta ADC with test circuitry 有权
标题翻译：带有测试电路的Σ-ΔADC
公开(公告)号：US08830098B2
公开(公告)日：2014-09-09
申请号：US13807632
申请日：2011-06-28
申请人： Salvador Mir , Haralampos Stratigopoulos , Matthieu Dubois
发明人： Salvador Mir , Haralampos Stratigopoulos , Matthieu Dubois
IPC分类号： H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： The invention concerns a sigma-delta switched capacitor analog to digital converter (ADC) having: an input line for receiving a signal to be converted; first, second and third inputs for respectively receiving first, second and third test voltages; and switching circuitry adapted to apply, during a test mode of the sigma-delta ADC, a ternary test signal to the input line by periodically selecting, based on a digital test control signal, one of the first, second or third test voltages to be applied to the input line.
摘要翻译：本发明涉及一种Σ-Δ开关电容器模数转换器（ADC），具有：用于接收要转换的信号的输入线; 分别接收第一，第二和第三测试电压的第一，第二和第三输入; 以及开关电路，其适于在Σ-ΔADC的测试模式期间，通过周期性地选择第一，第二或第三测试电压中的一个，基于数字测试控制信号将三态测试信号应用于输入线应用于输入线。

3. 发明申请

US20140025869A1 METHOD AND SYSTEM FOR IMPROVING A CONTROL OF A LIMIT ON WRITING CYCLES OF AN IC CARD 审中-公开
标题翻译：用于改善IC卡周期限制控制的方法和系统
公开(公告)号：US20140025869A1
公开(公告)日：2014-01-23
申请号：US13976686
申请日：2011-12-23
申请人： Amedeo Veneroso , Francesco Varone , Vitantonio Distasio , Pasquale Vastano
发明人： Amedeo Veneroso , Francesco Varone , Vitantonio Distasio , Pasquale Vastano
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0238 , G06F2212/1036 , G06F2212/7211
摘要： The present invention relates to a method and system for controlling a number of writing cycles supported by a cell or portion (11) of a non volatile memory (4) of an IC Card (10), including the steps of counting write accesses to the memory portion (11) and storing a first counter (21) of the write accesses in another portion (21) of said non volatile memory (4). The method comprises coupling the first counter (21) to a second counter or value (31) associated to a RAM (4) (Random Access Memory) of the IC Card (10), wherein the second counter or value (31) is updated each time the write accesses occur on said cell or portion (11) to be controlled and the first counter (21) is written in the another portion of non volatile memory only when the second counter or value (21) corresponds to a predetermined value.
摘要翻译：本发明涉及一种用于控制由IC卡（10）的非易失性存储器（4）的单元或部分（11）支持的写入周期数量的方法和系统，包括以下步骤：对对存储部分（11），并且将所述写访问的第一计数器（21）存储在所述非易失性存储器（4）的另一部分（21）中。该方法包括将第一计数器（21）耦合到与IC卡（10）的RAM（4）（随机存取存储器）相关联的第二计数器或值（31），其中第二计数器或值（31）被更新每当写入访问发生在要被控制的所述单元或部分（11）上时，只有当第二计数器或值（21）对应于预定值时，才将第一计数器（21）写入非易失性存储器的另一部分。

4. 发明授权

US08451035B2 Synthesizable DLL on system-on-chip 有权
标题翻译：片上系统上的合成DLL
公开(公告)号：US08451035B2
公开(公告)日：2013-05-28
申请号：US12969220
申请日：2010-12-15
申请人： Prateek Sikka , Rajesh Chopra , Manoj Yadav
发明人： Prateek Sikka , Rajesh Chopra , Manoj Yadav
IPC分类号： H03L7/06
CPC分类号： H03K5/135 , G06F17/5045
摘要： The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.
摘要翻译：本公开提供了用于调试的片上系统（SoC）上的仿真器映射过程。该实现减少了手动干预，并使仿真映射过程非常通用和独立于技术，从而减少了整个项目周期的时间。在本公开中，通过与可合成的延迟逻辑模块并联配置模拟延迟锁定环模块，包含模拟延迟锁定环路的SoC适于仿真。此外，提供选择逻辑以一次选择模块中的任何一个。

5. 发明申请

US20130110898A1 APPARATUS FOR SIGNAL PROCESSING 有权
标题翻译：信号处理装置
公开(公告)号：US20130110898A1
公开(公告)日：2013-05-02
申请号：US13468924
申请日：2012-05-10
申请人： Ankur BAL , Anupam JAIN , Neha BHARGAVA
发明人： Ankur BAL , Anupam JAIN , Neha BHARGAVA
IPC分类号： G06F17/10
CPC分类号： H03H17/0664
摘要： A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.
摘要翻译：信号处理器包括一个或多个存储体，其中每个存储体存储滤波器系数; 和一个或多个系数多路复用器单元; 每个系数多路复用器单元与存储器组相关联，并且基于所接收的输入采样的数量来检索滤波器系数。处理器包括一个或多个乘法和累积（MAC）单元，每个MAC单元与系数多路复用器单元相关联，并且确定所检索的滤波器系数与输入采样的乘积; 检索存储在相关联寄存器中的先前值; 计算以前的值和乘积的总和; 并将求和存储在相关联的寄存器中。处理器包括输出多路复用器单元，用于选择寄存器，并将存储在寄存器中的值提供为输出。

6. 发明授权

US09324399B2 System and method for a level shifting decoder 有权
标题翻译：电平转换解码器的系统和方法
公开(公告)号：US09324399B2
公开(公告)日：2016-04-26
申请号：US14183225
申请日：2014-02-18
申请人： STMicroelectronics International N.V. , STMicroelectronics S.r.l
发明人： Marco Pasotti , Abhishek Lal , Rajat Kulshrestha
IPC分类号： G11C8/10 , G11C8/08 , G11C8/06 , G11C16/12
CPC分类号： G11C8/10 , G11C8/06 , G11C8/08 , G11C16/12
摘要： According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.
摘要翻译：根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有输入耦合以接收地址信号和耦合到缓冲器的输出。

7. 发明授权

US11209482B1 Methods and devices for testing comparators 有权
公开(公告)号：US11209482B1
公开(公告)日：2021-12-28
申请号：US17107370
申请日：2020-11-30
申请人： STMicroelectronics International NV
发明人： Vivek Mohan Sharma , Deepak Baranwal , Amulya Pandey
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3193 , G06F11/22
摘要： A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.

8. 发明授权

US08934628B2 Method to de-correlate electric signals emitted by an IC card 有权
标题翻译：将IC卡发出的电信号去相关的方法
公开(公告)号：US08934628B2
公开(公告)日：2015-01-13
申请号：US13339859
申请日：2011-12-29
申请人： Rosario Bosco , Vincenzo Pascariello
发明人： Rosario Bosco , Vincenzo Pascariello
IPC分类号： G06F21/00 , G06F21/60 , G06F21/55 , G06F21/72
CPC分类号： G06F21/558 , G06F21/725 , G06F21/755
摘要： A method is to de-correlate electric signals emitted by an IC Card during computations as well as sensitive data involved in such computations. The method includes executing functions introducing respective electric signals which do not involve the sensitive data. Each of the functions is triggered by a timer having a value which is different at each step of executing the functions.
摘要翻译：一种方法是在计算过程中将由IC卡发出的电信号与在此类计算中涉及的敏感数据相关联。该方法包括执行引入不涉及敏感数据的各个电信号的功能。每个功能由具有在执行功能的每个步骤不同的值的定时器触发。

9. 发明授权

US10180324B2 Microelectromechanical gyroscope with rejection of disturbances and method of sensing an angular rate 有权
公开(公告)号：US10180324B2
公开(公告)日：2019-01-15
申请号：US15197414
申请日：2016-06-29
申请人： STMICROELECTRONICS S.R.L. , STMICROELECTRONICS, INC. , STMICROELECTRONICS INTERNATIONAL N.V.
发明人： Carlo Valzasina , Huantong Zhang , Matteo Fabio Brunetto , Gert Ingvar Andersson , Erik Daniel Svensson , Nils Einar Hedenstierna
IPC分类号： G01C19/56 , G01P9/04 , G01C19/574 , G01C19/5719 , G01C19/5776
摘要： A gyroscope includes a substrate, a first structure, a second structure and a third structure elastically coupled to the substrate and movable along a first axis. The first and second structure are arranged at opposite sides of the third structure with respect to the first axis A driving system is configured to oscillate the first and second structure along the first axis in phase with one another and in phase opposition with the third structure. The first, second and third structure are provided with respective sets of sensing electrodes, configured to be displaced along a second axis perpendicular to the first axis in response to rotations of the substrate about a third axis perpendicular to the first axis and to the second axis.

10. 发明申请

US20130328150A1 ADJUSTABLE AVALANCHE DIODE IN AN INTEGRATED CIRCUIT 有权
标题翻译：在一体化电路中可调节的AVALANCHE二极管
公开(公告)号：US20130328150A1
公开(公告)日：2013-12-12
申请号：US13895715
申请日：2013-05-16
申请人： STMicroelectronics International NV
发明人： Raul Andres BIANCHI , Pascal FONTENEAU
IPC分类号： H01L31/0256 , H01L27/144 , H01L31/18
CPC分类号： H01L31/0256 , H01L27/144 , H01L29/0684 , H01L29/66113 , H01L29/866 , H01L31/1892
摘要： An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.
摘要翻译：一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

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