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1. 发明授权

US08995139B2 Circuit device and method of manufacturing the same 有权
标题翻译：电路装置及其制造方法
公开(公告)号：US08995139B2
公开(公告)日：2015-03-31
申请号：US13331784
申请日：2011-12-20
申请人： Hideyuki Sakamoto
发明人： Hideyuki Sakamoto
IPC分类号： H05K5/00 , H01L23/31 , H05K3/28 , H01L21/56 , H05K3/00
CPC分类号： H01L23/3107 , B29C45/14008 , B29C45/14819 , B29L2031/3425 , H01L21/565 , H01L2224/48091 , H01L2224/73265 , H01L2924/13055 , H01L2924/13091 , H01L2924/19105 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K2201/09154 , H05K2203/1316 , H05K2203/1545 , H01L2924/00014 , H01L2924/00
摘要： Provided is a circuit device in which encapsulating resin to encapsulate a circuit board is optimized in shape, and a method of manufacturing the circuit device. A hybrid integrated circuit device, which is a circuit device according to the present invention includes a circuit board, a circuit element mounted on a top surface of the circuit board, and encapsulating resin encapsulating the circuit element, and coating the top surface, side surfaces, and a bottom surface of the circuit board. In addition, the encapsulating resin is partly recessed and thereby provided with recessed areas at two sides of the circuit board. The providing of the recessed areas reduces the amount of resin to be used, and prevents the hybrid integrated circuit device from being deformed by the cure shrinkage of the encapsulating resin.
摘要翻译：提供一种电路装置，其中密封电路板的封装树脂的形状优化，以及制造电路装置的方法。作为根据本发明的电路装置的混合集成电路装置包括电路板，安装在电路板的顶表面上的电路元件和封装电路元件的封装树脂，并且将顶表面，侧表面，以及电路板的底面。此外，封装树脂部分凹陷，从而在电路板的两侧设置有凹陷区域。凹陷区域的设置减少了使用的树脂的量，并且防止混合集成电路器件由于封装树脂的固化收缩而变形。

2. 发明授权

US07920424B2 Scalable electrically eraseable and programmable memory (EEPROM) cell array 有权
标题翻译：可扩展的电可擦除和可编程存储器（EEPROM）单元阵列
公开(公告)号：US07920424B2
公开(公告)日：2011-04-05
申请号：US12389972
申请日：2009-02-20
申请人： Sorin S. Georgescu , A. Peter Cosmin
发明人： Sorin S. Georgescu , A. Peter Cosmin
IPC分类号： G11C16/04
CPC分类号： H01L29/7883 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
摘要翻译：非易失性存储器（NVM）系统包括以双阱结构制造的多个NVM单元。每个NVM单元包括存取晶体管和NVM晶体管，其中存取晶体管具有与NVM晶体管的源极区域连续的漏极区域。阵列列中的每个NVM晶体管的漏极区域共同连接到相应的位线。阵列的一行中的每个NVM晶体管的控制栅极通常连接到相应的字线。阵列中每个存取晶体管的源极区域通常耦合。 NVM单元被编程和擦除，而不必在存取晶体管的栅极电介质层上施加高编程电压VPP。因此，NVM电池可以缩小到0.35微米以下的几何尺寸。

3. 发明授权

US07902075B2 Semiconductor trench structure having a sealing plug and method 有权
标题翻译：具有密封塞和方法的半导体沟槽结构
公开(公告)号：US07902075B2
公开(公告)日：2011-03-08
申请号：US12206541
申请日：2008-09-08
申请人： Gordon M. Grivna , Gary H. Loechelt , John Michael Parsey, Jr. , Mohammed Tanvir Quddus
发明人： Gordon M. Grivna , Gary H. Loechelt , John Michael Parsey, Jr. , Mohammed Tanvir Quddus
IPC分类号： H01L21/00
CPC分类号： H01L29/7813 , H01L21/76232 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
摘要翻译：在一个实施例中，形成具有沟槽结构的半导体器件。沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。在一个实施例中，单晶半导体插塞密封沟槽以形成密封的芯。

4. 发明授权

US07851852B2 Method of forming a low capacitance semiconductor device and structure therefor 有权
标题翻译：形成低电容半导体器件的方法及其结构
公开(公告)号：US07851852B2
公开(公告)日：2010-12-14
申请号：US12574934
申请日：2009-10-07
申请人： Prasad Venkatraman
发明人： Prasad Venkatraman
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/402 , H01L29/66719 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
摘要翻译：在一个实施例中，晶体管形成为具有在栅极结构中具有开口的栅极结构。在开口的至少侧壁上形成绝缘体，并且在绝缘体上形成导体。

5. 发明授权

US07830714B2 Non-volatile memory with high reliability 有权
标题翻译：非易失性存储器具有高可靠性
公开(公告)号：US07830714B2
公开(公告)日：2010-11-09
申请号：US12106777
申请日：2008-04-21
申请人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
发明人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
摘要翻译：非易失性存储器（NVM）系统包括一组NVM单元，每个NVM单元包括：NVM晶体管; 将NVM晶体管耦合到对应的位线的存取晶体管; 以及将NVM晶体管耦合到公共源的源极选择晶体管。 NVM单元由包括擦除阶段和程序阶段的两相操作来写入。在擦除和编程阶段期间，将一组常见的位线电压施加到位线。接入晶体管导通，并且在擦除和编程阶段期间，源选择晶体管截止。在擦除阶段期间，将第一控制电压施加到NVM晶体管的控制栅极，并且在编程阶段期间将第二控制电压施加到NVM晶体管的控制栅极。在这些条件下，Fowler-Nordheim隧道掘进作业的平均要求数量减少了。

6. 发明授权

US07679874B2 Power overload detection method and structure therefor 有权
标题翻译：电力过载检测方法及其结构
公开(公告)号：US07679874B2
公开(公告)日：2010-03-16
申请号：US11188093
申请日：2005-07-25
申请人： George H. Barbehenn , John D. Stone
发明人： George H. Barbehenn , John D. Stone
IPC分类号： H02H3/00
CPC分类号： H02H7/1227 , H02M1/32 , H02M3/33507
摘要： In one embodiment, the bulk input voltage is used to form a reference signal that is used for controlling a switching power supply system to operate in a power overload operating mode.
摘要翻译：在一个实施例中，大容量输入电压用于形成用于控制开关电源系统在功率过载操作模式下操作的参考信号。

7. 发明授权

US07646028B2 LED driver with integrated bias and dimming control storage 有权
标题翻译： LED驱动器集成偏置和调光控制存储
公开(公告)号：US07646028B2
公开(公告)日：2010-01-12
申请号：US10463979
申请日：2003-06-17
申请人： Anthony G. Russell , Gelu Voicu
发明人： Anthony G. Russell , Gelu Voicu
IPC分类号： H01L27/15
CPC分类号： H05B33/0815 , H05B33/0848 , H05B33/0854
摘要： A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any control input from off-chip components or signals. Therefore, the space requirements for LED circuits that make use of the LED driver IC can be minimized. Also, the non-volatile memory storage of settings data eliminates the need for an initialization or configuration input each time the LED driver IC is powered on. The non-volatile memory can be a one-time programmable memory or can be a reprogrammable memory.
摘要翻译： LED驱动器IC包括用于控制一个或多个LED驱动器参数的控制模块和用于存储该控制模块的设置数据的非易失性存储器。控制模块完全集成到LED驱动器IC中，不需要来自芯片外部件或信号的任何控制输入。因此，可以使利用LED驱动器IC的LED电路的空间要求最小化。此外，每当LED驱动器IC通电时，设置数据的非易失性存储器存储消除了初始化或配置输入的需要。非易失性存储器可以是一次性可编程存储器，也可以是可再编程存储器。

8. 发明授权

US07642754B2 Method of forming a voltage regulator and structure therefor 有权
标题翻译：形成电压调节器及其结构的方法
公开(公告)号：US07642754B2
公开(公告)日：2010-01-05
申请号：US11448881
申请日：2006-06-08
申请人： Stephen W. Dow , Praveen Manapragada , David F. Moeller
发明人： Stephen W. Dow , Praveen Manapragada , David F. Moeller
IPC分类号： H02J7/00
CPC分类号： H02M1/36
摘要： In one embodiment, a voltage regulator uses a first current to charge a by-pass capacitor for a first time period and uses a second current after the first time period.
摘要翻译：在一个实施例中，电压调节器使用第一电流对第一时间段的旁路电容器进行充电，并且在第一时间段之后使用第二电流。

9. 发明授权

US07602054B2 Method of forming a molded array package device having an exposed tab and structure 有权
标题翻译：形成具有暴露突片和结构的模制阵列封装装置的方法
公开(公告)号：US07602054B2
公开(公告)日：2009-10-13
申请号：US11243195
申请日：2005-10-05
申请人： James P. Letterman, Jr. , Kent L. Kime , Joseph K. Fauty
发明人： James P. Letterman, Jr. , Kent L. Kime , Joseph K. Fauty
IPC分类号： H01L23/02
CPC分类号： H01L21/561 , H01L23/49524 , H01L23/49562 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.
摘要翻译：在一个实施例中，一种用于形成模制扁平封装型封装的方法包括将电子芯片附接到阵列引线框架，该阵列引线框架包括具有突片部分和多个引线的多个细长标记部分。该方法还包括将电子芯片连接到特定引线，然后模制阵列引线框架，同时使部分引线暴露以形成模制阵列结构。然后将模制的阵列结构分离以提供具有用于插入安装和暴露的突片部分的暴露引线的模制扁平封装型封装。在替代实施例中，分离步骤产生具有暴露的突片部分的无引线配置。

10. 发明授权

US07528551B2 LED control system 有权
标题翻译： LED控制系统
公开(公告)号：US07528551B2
公开(公告)日：2009-05-05
申请号：US11678793
申请日：2007-02-26
申请人： Alan R. Ball
发明人： Alan R. Ball
IPC分类号： H05B41/16
CPC分类号： H05B33/0821 , H05B33/0815
摘要： In one embodiment, an LED system is controlled to have a substantially unity power factor.
摘要翻译：在一个实施例中，LED系统被控制为具有基本上一致的功率因数。

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