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1. 发明授权

US09030860B2 Power up detection system for a memory device 有权
标题翻译：用于存储设备的上电检测系统
公开(公告)号：US09030860B2
公开(公告)日：2015-05-12
申请号：US13894824
申请日：2013-05-15
申请人： Sidense Corp.
发明人： Steven Smith
IPC分类号： G11C17/00 , G11C17/18 , A61F13/15
CPC分类号： G11C17/18 , A61F13/15764 , A61F13/15804
摘要： A power up detection method for a memory device and a memory device are disclosed. In a first phase, a test word is read from a read-only memory (ROM) row of a memory array of the memory device, and the test word is compared to predetermined ROM row data. If the test word matches the predetermined ROM row data, a second phase may be performed. In the second phase, first user data is read from a user-programmed row of the memory array at a first time. Second user data is read from the user-programmed row of the memory array at a second time different from the first time. The first user data is compared to the second user data. Successful power up of the memory device is determined when the first user data matches the second user data.
摘要翻译：公开了一种用于存储器件和存储器件的上电检测方法。在第一阶段中，从存储器件的存储器阵列的只读存储器（ROM）行读取测试字，并将测试字与预定的ROM行数据进行比较。如果测试字符与预定的ROM行数据匹配，则可以执行第二阶段。在第二阶段中，第一次从存储器阵列的用户编程行读取第一用户数据。与第一次不同的第二时间从用户编程的存储器阵列行读取第二用户数据。将第一用户数据与第二用户数据进行比较。当第一用户数据与第二用户数据匹配时确定存储设备的成功上电。

2. 发明申请

US20140146625A1 REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的冗余系统
公开(公告)号：US20140146625A1
公开(公告)日：2014-05-29
申请号：US14162380
申请日：2014-01-23
申请人： SIDENSE CORP.
发明人： Wlodek KURJANOWICZ , Mourad ABDAT
IPC分类号： G11C29/04
CPC分类号： G11C16/26 , G11C16/04 , G11C17/16 , G11C29/787 , G11C29/82
摘要： A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.
摘要翻译：描述了非易失性存储器（NVM）的冗余方案。该冗余方案提供了在非易失性存储器中使用有缺陷的单元以增加产量的装置。当在小区分组中检测到有缺陷的小区时，该算法基于将被编程的数据的程序数据反转到小区分组。有缺陷的单元被偏置到“1”或“0”逻辑状态，这些状态被有效地预设为存储其偏置的逻辑状态。要存储在具有与单元的偏置逻辑状态互补的逻辑状态的缺陷单元的数据位导致程序数据被反转和编程。反转状态位被编程为指示编程数据的反转状态。在读出期间，反转状态位使得存储的数据被重新反转成其原始的程序数据状态。

3. 发明授权

US08313987B2 Anti-fuse memory cell 有权
标题翻译：防熔丝存储单元
公开(公告)号：US08313987B2
公开(公告)日：2012-11-20
申请号：US13219215
申请日：2011-08-26
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： H01L21/82
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.
摘要翻译：具有可变厚度栅极电介质的反熔丝存储单元。可变厚度电介质具有厚部分和薄部分，其中薄部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。薄部分的形状可以是矩形或三角形。反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极电介质的厚度基本上与反熔丝晶体管的可变厚度栅极电介质的厚部相同。

4. 发明授权

US07944727B2 Mask programmable anti-fuse architecture 有权
标题翻译：面罩可编程反熔丝架构
公开(公告)号：US07944727B2
公开(公告)日：2011-05-17
申请号：US12306114
申请日：2007-12-20
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C17/10 , H01L27/0203 , H01L27/112
摘要： A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit.
摘要翻译：具有连接到字线和位线的掩模可编程和一次性可编程存储器单元的存储器阵列。存储器阵列的所有存储单元被配置为一次性可编程存储器单元。任何数量的这些一次性可编程存储器单元通过掩模编程（例如扩散掩模编程或接触/通孔掩模编程）可转换成掩模可编程存储器单元。这种混合存储器阵列的制造被简化，因为两种类型的存储器单元由相同的材料构成，因此仅需要一组常规的制造工艺步骤。掩模可编程存储单元的无意的用户编程被编程锁定电路所禁止。

5. 发明授权

US07940595B2 Power up detection system for a memory device 有权
标题翻译：用于存储设备的上电检测系统
公开(公告)号：US07940595B2
公开(公告)日：2011-05-10
申请号：US12306940
申请日：2007-12-20
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C7/00
CPC分类号： G11C29/52 , G11C5/143 , G11C16/3454 , G11C16/3459 , G11C17/14 , G11C17/16 , G11C17/165 , G11C19/00 , G11C29/027 , G11C2029/0407
摘要： A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.
摘要翻译：用于存储器件的上电检测系统。两行存储器单元被编程为包括具有任意大小的数据字。第二行中的字是第一行中单词的单位移位版本，使得每个位沿预定方向移位一位位置。第一个字的位从第一行读取到数据寄存器的寄存器级的从锁存器，然后移入数据寄存器的下一个寄存器级的主锁存器。第二个字的位从第二行读入寄存器级的从锁存器。数据比较逻辑比较存储在每个寄存器级的主锁存器和从锁存器中的数据，并且提供指示第一锁存器和第二锁存器之间的匹配数据的信号，从而指示存储器件的成功上电。

6. 发明授权

US07764532B2 High speed OTP sensing scheme 有权
标题翻译：高速OTP感应方案
公开(公告)号：US07764532B2
公开(公告)日：2010-07-27
申请号：US12389933
申请日：2009-02-20
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

7. 发明授权

US09870810B2 Method and system for power signature suppression in memory devices 有权
公开(公告)号：US09870810B2
公开(公告)日：2018-01-16
申请号：US15247050
申请日：2016-08-25
申请人： Sidense Corp.
发明人： Wlodek Kurjanowicz , Betina Hold
IPC分类号： G11C7/10 , G11C7/22 , G11C7/06
CPC分类号： G11C7/222 , G11C7/065 , G11C7/1006 , G11C7/1048 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1075 , G11C7/24 , G11C29/76 , G11C2207/108
摘要： A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

8. 发明授权

US09275753B2 Circuit and method for reducing write disturb in a non-volatile memory device 有权
标题翻译：用于减少非易失性存储器件中的写入干扰的电路和方法
公开(公告)号：US09275753B2
公开(公告)日：2016-03-01
申请号：US13896712
申请日：2013-05-17
申请人： SIDENSE CORP.
发明人： Steven Smith
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C17/16
摘要： An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line.
摘要翻译：公开了一种用于非易失性存储器阵列的有源预充电电路，其在编程期间最小化对未选择的存储器单元的写入干扰。在编程周期中，所有位线都被预充电到程序禁止电压电平，并且在预充电操作和随后的编程操作中，通过耦合到每个位线的电流或电压源来保持在程序禁止电压电平。在编程操作中，连接到要编程的存储器单元的位线被驱动到诸如VSS的编程电平，而有效预充电电路被使能以使能其编程。由于其他未选择的位线保持在程序禁止电压电平，当编程电压由字线提供时，它们不会被无意编程。

9. 发明授权

US09129687B2 OTP memory cell having low current leakage 有权
标题翻译： OTP存储单元具有低电流泄漏
公开(公告)号：US09129687B2
公开(公告)日：2015-09-08
申请号：US13504295
申请日：2010-10-29
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C17/16 , H01L27/112
CPC分类号： G11C17/16 , H01L27/112 , H01L27/11206
摘要： A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.
摘要翻译：具有双阱的一次性可编程存储单元，以在减少电流泄漏的同时改善电介质击穿。存储单元使用用于核心和I / O（输入/输出）电路的标准CMOS工艺制造。具有存取晶体管和反熔丝器件的双晶体管存储单元或具有双厚度栅极氧化物114和116的单晶体管存储单元100形成在双阱102和104中。双阱的类型与彼此可以是N型阱102，而另一个可以是P型阱104.抗熔丝器件由薄栅极氧化物形成，并且与用于核心电路的阱类似。存取晶体管形成有厚栅极氧化物，并且类似于用于I / O电路的阱。

10. 发明授权

US08767433B2 Methods for testing unprogrammed OTP memory 有权
标题翻译：测试未编程OTP内存的方法
公开(公告)号：US08767433B2
公开(公告)日：2014-07-01
申请号：US13412500
申请日：2012-03-05
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , G11C29/027 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.
摘要翻译：用于测试未编程单晶体管和两晶体管反熔丝存储单元的方法包括通过将连接到被测电池的位线的电压特性与具有预定电压特性的参考位线进行比较来测试单元与位线的连接。一些方法可以使用具有与正常存储器单元的存取晶体管相同配置的存取晶体管的测试单元，但是省略在正常存储单元中发现的反熔丝器件，用于测试正常存储器单元与位线这样的测试单元可用于进一步测试，用于确定字线电压与位线相对于正在测试的正常存储器单元的电容耦合水平。

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