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1. 发明授权

US09767867B2 Methods of communicating to different types of memory modules in a memory channel 有权
公开(公告)号：US09767867B2
公开(公告)日：2017-09-19
申请号：US14016202
申请日：2013-09-02
申请人： Virident Systems, LLC
发明人： Kenneth Alan Okin , George Moussa , Kumar Ganapathy , Vijay Karamcheti , Rajesh Parekh
IPC分类号： G11C7/10 , G06F13/16 , G11C5/04
CPC分类号： G11C7/1072 , G06F13/1694 , G11C5/04 , Y02D10/14
摘要： A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

2. 发明授权

US09513695B2 Methods of managing power in network computer systems 有权
标题翻译：网络计算机系统中的电源管理方法
公开(公告)号：US09513695B2
公开(公告)日：2016-12-06
申请号：US13952567
申请日：2013-07-26
申请人： Virident Systems, Inc.
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
IPC分类号： G06F12/02 , G06F1/32 , G06F3/06 , G06F9/50
CPC分类号： G06F1/329 , G06F1/3209 , G06F1/3287 , G06F3/061 , G06F3/0625 , G06F3/0638 , G06F3/0653 , G06F3/0674 , G06F3/0689 , G06F9/5094 , Y02D10/154 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
摘要翻译：在本发明的一个实施例中，公开了一种存储装置。存储装置包括存储器阵列，块读/写控制器和随机存取读存储控制器。存储器阵列是块读/写可访问和随机读取可访问的。块读/写控制器耦合在存储器阵列和外部互连之间。块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

3. 发明授权

US09262334B2 Seamless application access to hybrid main memory 有权
标题翻译：无缝应用访问混合主存
公开(公告)号：US09262334B2
公开(公告)日：2016-02-16
申请号：US14330930
申请日：2014-07-14
申请人： Virident Systems Inc.
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/00 , G06F12/10 , G06F9/50 , G06F12/08 , G06F12/12 , G06F3/06 , G06F13/16 , G06F12/02 , G06F12/14
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

4. 发明申请

US20140258653A1 INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY 有权
标题翻译：从对称和非对称存储器集成数据
公开(公告)号：US20140258653A1
公开(公告)日：2014-09-11
申请号：US14047627
申请日：2013-10-07
申请人： Virident Systems Inc.
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/12
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.
摘要翻译：存储在主存储器的对称和非对称存储器组件内的数据通过将第一数据识别为具有适于存储在非对称存储器组件中的访问特性而被集成。第一数据被包括在要写入非对称存储器组件的数据的集合中。在要写入非对称存储器组件的数据集合内识别数据量。数据量在数据集合中被比较到一个体积阈值，以确定对非对称存储器组件的写入写入是否被数据量所证明。如果合理，数据的收集将被加载到非对称存储器组件。

5. 发明申请

US20140258603A1 ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY 有权
标题翻译：混合主存储器中的不对称存储器迁移
公开(公告)号：US20140258603A1
公开(公告)日：2014-09-11
申请号：US14047603
申请日：2013-10-07
申请人： Virident Systems Inc.
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy , Ashish Singhai , Rajesh Parekh
IPC分类号： G06F12/08
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
摘要翻译：通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来管理主存储器。存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件中的一个，并且访问指示如何与虚拟地址相关联的数据被访问的存储器使用特性。存储器控制器确定与虚拟地址具有适合于主存储器的非对称存储器组件的访问特征，并将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。在加载和使用存储器管理单元之后，从应用程序接收到用于读取与虚拟地址相关联的数据的命令，并且从非对称存储器组件检索与虚拟地址相关联的数据。

6. 发明授权

US08745314B1 Methods for a random read and read/write block accessible memory 有权
标题翻译：随机读取和写入块可访问存储器的方法
公开(公告)号：US08745314B1
公开(公告)日：2014-06-03
申请号：US12490930
申请日：2009-06-24
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F13/1694 , G06F2212/211
摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
摘要翻译：在本发明的一个实施例中，公开了一种存储装置。存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。存储器阵列是块读/写可访问和随机读取可访问的。块读/写控制器耦合在存储器阵列和外部互连之间。块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

7. 发明授权

US08677037B1 Memory apparatus for early write termination and power failure 有权
标题翻译：用于早期写入终止和电源故障的存储设备
公开(公告)号：US08677037B1
公开(公告)日：2014-03-18
申请号：US13163461
申请日：2011-06-17
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
IPC分类号： G06F13/12
CPC分类号： G06F13/1642 , G06F13/1657 , G06F13/1694
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译：在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

8. 发明授权

US08650343B1 Methods for upgrading, diagnosing, and maintaining replaceable non-volatile memory 有权
标题翻译：升级，诊断和维护可更换的非易失性存储器的方法
公开(公告)号：US08650343B1
公开(公告)日：2014-02-11
申请号：US13163571
申请日：2011-06-17
申请人： Ruban Kanapathippillai , Ashwin Narasimha , Kenneth A. Okin , Vijay Karamcheti
发明人： Ruban Kanapathippillai , Ashwin Narasimha , Kenneth A. Okin , Vijay Karamcheti
IPC分类号： G06F13/12 , G06F12/00
CPC分类号： G06F13/1694 , G06F13/1657 , Y02D10/14
摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
摘要翻译：在本发明的一个实施例中，公开了一种可替换的存储装置。可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。

9. 发明授权

US08429318B1 Methods for early write termination into non-volatile memory with metadata write operations 有权
标题翻译：使用元数据写操作将早期写入终止到非易失性存储器的方法
公开(公告)号：US08429318B1
公开(公告)日：2013-04-23
申请号：US13163493
申请日：2011-06-17
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
IPC分类号： G06F13/12
CPC分类号： G06F13/1657
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译：在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

10. 发明申请

US20120254577A1 Managing Memory Systems Containing Components with Asymmetric Characteristics 有权
公开(公告)号：US20120254577A1
公开(公告)日：2012-10-04
申请号：US13493766
申请日：2012-06-11
申请人： Kenneth A. Okin , Vijay Karamcheti
发明人： Kenneth A. Okin , Vijay Karamcheti
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F11/1658 , G06F11/20 , G06F12/0246 , G06F12/06 , G06F12/08 , G06F12/10 , G06F2212/1032 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G11C16/3418 , G11C16/3427
摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

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