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1. 发明申请

US20180106864A1 METHOD AND APPARATUS FOR HIGH FREQUENCY ANALOG-TO-DIGITAL CONVERSION 审中-公开
公开(公告)号：US20180106864A1
公开(公告)日：2018-04-19
申请号：US15689237
申请日：2017-08-29
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Nicolas Moeneclaey
IPC分类号： G01R31/3193 , G01R31/3187 , H04L7/00 , H03L7/18 , H03L7/085 , G01R31/317
CPC分类号： G01R31/31937 , G01R31/31718 , G01R31/3187 , H01L27/14643 , H03L7/085 , H03L7/18 , H03M1/00 , H03M1/12 , H03M2201/4233 , H04L7/0025 , H04N3/155 , H04N5/335 , H04N5/3765 , H04N5/378
摘要： A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by π/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

2. 发明授权

US09891267B2 Kernel based cluster fault analysis 有权
公开(公告)号：US09891267B2
公开(公告)日：2018-02-13
申请号：US15181649
申请日：2016-06-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Nikolas Bradley Sumikawa , Chen He
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185 , G01R31/26 , G01R31/01 , G01R31/18 , H01L21/66
CPC分类号： G01R31/18 , G01R31/01 , G01R31/26 , G01R31/2894 , G01R31/31718 , G01R31/318511 , G01R31/31937 , H01L22/00
摘要： A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

3. 发明授权

US09865486B2 Timing/power risk optimized selective voltage binning using non-linear voltage slope 有权
公开(公告)号：US09865486B2
公开(公告)日：2018-01-09
申请号：US15083692
申请日：2016-03-29
申请人： GLOBALFOUNDRIES INC.
发明人： Igor Arsovski , Jeanne P. Bickford , Mark W. Kuemerle , Susan K. Lichtensteiger , Jeanne H. Raymond
IPC分类号： G01R31/26 , H01L21/66 , H01L21/67 , G06F17/50 , G01R31/28
CPC分类号： H01L21/67271 , G01R31/2882 , G01R31/3004 , G01R31/31718 , G06F17/5036 , G06F17/5081 , G06F2217/10 , G06F2217/78 , G06F2217/84 , H01L21/67253 , H01L22/14
摘要： Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.

4. 发明申请

US20170356955A1 KERNEL BASED CLUSTER FAULT ANALYSIS 有权
公开(公告)号：US20170356955A1
公开(公告)日：2017-12-14
申请号：US15181649
申请日：2016-06-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Nikolas Bradley SUMIKAWA , Chen HE
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/18 , G01R31/01 , G01R31/26 , G01R31/2894 , G01R31/31718 , G01R31/318511 , G01R31/31937 , H01L22/00
摘要： A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

5. 发明申请

US20170262557A1 METHOD OF ANALYZING SEMICONDUCTOR DEVICES AND ANALYSIS APPARATUS FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20170262557A1
公开(公告)日：2017-09-14
申请号：US15346979
申请日：2016-11-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： KATSUHIRO SHIMAZU , IN-SUNG HWANG , KWANG-OK JEONG
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G01R31/2894 , G01R31/31718 , G06F17/5081
摘要： In a method of analyzing a semiconductor device, output values of semiconductor devices are measured, population data including the output values in connection with values of design attributes of the semiconductor devices is determined, outlier output values are extracted from among the output values included in the population data to determine discriminated data, and a weak value of a weak design attribute, which causes the outlier output values, is determined based on a difference between a ratio of a number of outlier output values, which are related with respective values of the design attributes, to a total number of the outlier output values included in the discriminated data, and a ratio of a number of output values, which are related with respective values of the design attributes, to a total number of the output values included in the population data.

6. 发明授权

US09733306B2 Remote evaluation tool 有权
公开(公告)号：US09733306B2
公开(公告)日：2017-08-15
申请号：US14935644
申请日：2015-11-09
申请人： ANALOG DEVICES GLOBAL
发明人： Richard E. Schreier , Alexander Newcombe , Ross Willett , Andre Straker
IPC分类号： G06F11/00 , G01R31/28 , G01R31/317 , G01R31/3177 , H04L29/08 , G06F11/22
CPC分类号： G01R31/31718 , G01R31/31707 , G01R31/31724 , G01R31/3177 , G01R31/318314 , G06F11/2294 , H04L67/02 , H04L67/10 , H04L67/125
摘要： Remote evaluation, e.g., web-based evaluation, lowers the evaluation barrier by allowing an engineer to gain experience with an integrated circuit (IC) using a client (e.g. a web browser) on a remote computer (e.g., a machine remote from the IC being evaluated but local to the engineer) to activate a test set-up that is maintained at a location that is far away from the engineer.

7. 发明申请

US20170102427A1 SEMICONDUCTOR TEST APPARATUS 审中-公开
公开(公告)号：US20170102427A1
公开(公告)日：2017-04-13
申请号：US15285849
申请日：2016-10-05
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-young LEE , Byoung-jun MIN , Jong-cheol LEE
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2601 , G01R31/2875 , G01R31/2893 , G01R31/31718
摘要： A semiconductor test apparatus includes: a tray housing unit configured to house a customer tray loading untested semiconductor chips, secondary semiconductor chips, and non-defective semiconductor chips; a loader configured to locate the untested semiconductor chips supplied from the tray housing unit on a loading set plate and load the untested semiconductor chips onto a test tray; a tester configured to test semiconductor chips loaded on the test tray; an unloader configured to unload semiconductor chips loaded on the test tray, classify the tested semiconductor chips, and locate the classified semiconductor chips on an unloading set plate; and a retest controller configured to transfer the secondary defective semiconductor chips and the non-defective semiconductor chips to the tray housing unit and transfer the first defective semiconductor chips to the loading set plate.

8. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

9. 发明授权

US09494650B2 Efficient method of retesting integrated circuits 有权
标题翻译：高效集成电路重新测试方法
公开(公告)号：US09494650B2
公开(公告)日：2016-11-15
申请号：US13833308
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.
摘要翻译：集成电路的高效生产测试。对一组集成电路进行第一次生产测试，并对测试组中的故障进行评估。具体地，分析第一测试的结果，使得具有可恢复故障的集成电路和具有不可恢复故障的集成电路被区分。基于分析结果集成了集成电路，实现了第二次生产测试。第二次生产测试根据分离测试集成电路，使得第二次生产测试仅限于具有可恢复故障的集成电路。接下来的生产测试将在第二次生产测试中使用新的测试程序，并将处理器箱指定为不具有集成电路的重新测试。

10. 发明授权

US09430603B1 Scaling voltages in relation to die location 有权
标题翻译：相对于模具位置调整电压
公开(公告)号：US09430603B1
公开(公告)日：2016-08-30
申请号：US14959346
申请日：2015-12-04
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Nazmul Habib , Kerim Kalafala
IPC分类号： G06F9/455 , G06F17/50 , G01R31/317
CPC分类号： G06F17/5081 , G01R31/31718 , G01R31/31725 , G06F17/5036 , G06F17/5068 , G06F2217/78
摘要： The method includes identifying, by one or more computer processors, a location that corresponds to an integrated circuit chip on a wafer. The method further includes identifying, by one or more computer processors, an on-chip variation of the integrated circuit chip. The method further includes determining, by one or more computer processes, a desired voltage for the integrated circuit chip based upon the identified on-chip variation of the integrated circuit chip. The method further includes adjusting, by one or more computer processors, the voltage of the integrated circuit chip via a voltage regulated on the integrated circuit chip based upon the determined desired voltage.
摘要翻译：该方法包括由一个或多个计算机处理器识别对应于晶片上的集成电路芯片的位置。该方法还包括由一个或多个计算机处理器识别集成电路芯片的片上变化。该方法还包括基于所识别的集成电路芯片的片上变化，通过一个或多个计算机处理确定集成电路芯片的期望电压。该方法还包括：通过一个或多个计算机处理器，基于所确定的期望电压，经由集成电路芯片上调节的电压来调整集成电路芯片的电压。

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