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1. 发明申请

US20180113757A1 Field Programmable Gate Array 审中-公开
公开(公告)号：US20180113757A1
公开(公告)日：2018-04-26
申请号：US15737549
申请日：2015-06-22
申请人： Hitachi, Ltd.
发明人： Teruaki SAKATA , Tsutomu YAMADA
IPC分类号： G06F11/08 , H03K19/177 , G01R31/3185
CPC分类号： G06F11/085 , B61L5/18 , G01R31/318519 , H03K19/173 , H03K19/17728 , H03K19/17744 , H03K19/1776 , H03K19/17776
摘要： An object of the invention is to provide a field programmable gate array which is able to prevent an inappropriate value from being output to the outside of an FPGA even when an SRAM-based programmable logic portion is out of order and to secure safety of a system. The field programmable gate array of the invention includes a hard macro CPU in which a circuit structure is fixed, a programmable logic in which a circuit structure is changeable, a diagnosis circuit which diagnoses an abnormality of the programmable logic, and a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side, and the hard macro CPU outputs a fail-safe signal which is an output of a safe side to the fail-sate interface circuit when an error is detected by the diagnosis circuit.

2. 发明授权

US09797946B2 Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs 有权
公开(公告)号：US09797946B2
公开(公告)日：2017-10-24
申请号：US14946543
申请日：2015-11-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318516 , G01R31/318519 , G01R31/318558 , G01R31/318561 , G01R31/3187
摘要： Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.

3. 发明申请

US20160188778A1 IMPLEMENTING SYSTEM IRRITATOR ACCELERATOR FPGA UNIT (AFU) RESIDING BEHIND A COHERENT ATTACHED PROCESSORS INTERFACE (CAPI) UNIT 有权
标题翻译：实现系统IRRITATOR ACCERERATOR FPGA单元（AFU）保留一个相邻的连接处理器接口（CAPI）单元
公开(公告)号：US20160188778A1
公开(公告)日：2016-06-30
申请号：US14585602
申请日：2014-12-30
申请人： International Business Machines Corporation
发明人： Jason D. Greenwood , Steven D. McJunkin , Paul E. Schardt , Nathaniel K. Tuen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G01R31/318519
摘要： A method and apparatus are provided for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit in a computer system. An AFU is implemented in an FPGA residing behind the CAPI unit, the AFU includes a system irritator accelerator. A processor configures the AFU and enables the AFU system irritator to execute. The AFU system irritator is replicated to create additional irritation and is re-programmable.
摘要翻译：提供了一种用于实现驻留在计算机系统中的相干附加处理器接口（CAPI）单元之后的系统刺激加速器现场可编程门阵列（FPGA）单元（AFU）的方法和装置。 AFU在位于CAPI单元后面的FPGA中实现，AFU包括系统刺激加速器。处理器配置AFU并使AFU系统刺激器能够执行。 AFU系统刺激器被复制以产生额外的刺激并且是可重新编程的。

4. 发明授权

US09310432B2 Method and system for measuring the impedance of the power distribution network in programmable logic device applications 有权
标题翻译：用于测量可编程逻辑器件应用中配电网络阻抗的方法和系统
公开(公告)号：US09310432B2
公开(公告)日：2016-04-12
申请号：US13465024
申请日：2012-05-06
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G01R27/00 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31721 , G01R31/318519
摘要： On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.
摘要翻译：通过仅配置和使用通常可用的逻辑块资源来执行可编程逻辑器件（PLD）（例如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD））的功率分布阻抗频率分布的裸片测量任何现有的可编程逻辑器件，无需内置专用电路。所有的测量都是在可编程逻辑器件内进行的，而无需外部仪器。在表征期间可以使用测量方法来选择去耦电容器或用于对现有系统进行故障排除，之后可重新配置可编程逻辑器件以执行任何其他用户定义的功能。

5. 发明授权

US09255968B2 Integrated circuit with a high-speed debug access port 有权
标题翻译：集成电路具有高速调试访问端口
公开(公告)号：US09255968B2
公开(公告)日：2016-02-09
申请号：US14087690
申请日：2013-11-22
申请人： Altera Corporation
发明人： Christopher D. Finan
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/318519 , G01R31/31705
摘要： An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit.
摘要翻译：具有高速调试访问端口的集成电路包括接口电路和接口电路中的专用调试端口。接口电路包括功能电路块，用于从耦合到集成电路的外部电路接收数据分组。专用调试端口耦合到功能电路块，并用于将接收到的数据分组发送到集成电路上的调试电路。接口电路可以包括外围组件互连快速（PCIe）接口电路。

6. 发明申请

US20160003902A1 SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS 有权
标题翻译：扫描链条设计，提高集成电路的可测性
公开(公告)号：US20160003902A1
公开(公告)日：2016-01-07
申请号：US14722377
申请日：2015-05-27
申请人： International Business Machines Corporation
发明人： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
摘要： A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
摘要翻译：公开了扫描链锁存电路，操作扫描链中的锁存电路的方法，以及其上存储有限定用于在半导体管芯上实例化的扫描链锁存电路的数据结构的计算机可读介质。在一个实施例中，扫描链锁存电路包括用于保存一个数据值的第一锁存器，用于保存另一个数据值的第二锁存器和多路复用器。一个数据值被应用于多路复用器的第一数据输入端，并且另一个数据值被应用于多路复用器的第二数据输入端。交替时钟信号被施加到多路复用器的选择输入端以控制多路复用器的输出，其中多路复用器的输出在保持在两个锁存器中的两个数据值之间以定义的频率切换。

7. 发明授权

US09176839B2 Bus transaction monitoring and debugging system using FPGA 有权
标题翻译：总线事务监控和调试系统采用FPGA
公开(公告)号：US09176839B2
公开(公告)日：2015-11-03
申请号：US13473650
申请日：2012-05-17
申请人： Ravishankar Rajarao , Senthil Kumar Balan
发明人： Ravishankar Rajarao , Senthil Kumar Balan
IPC分类号： G01R31/28 , G06F7/02 , H04J3/24 , H04J3/04 , G06F13/36 , G06F13/14 , G06F11/32 , G06F11/30
CPC分类号： G01R31/318519
摘要： The various embodiments herein provide a method and a system for providing a bus transaction monitoring and debugging using FPGA. The system comprises a first FPGA, a second FPGA, application software and a communication interface to connect the second FPGA with the application software. The second FPGA comprises a monitor RTL for tapping data signals from different levels of the first FPGA, a transaction based signal trigger for capturing the signals tapped at different levels of the RTL, a monitor data interface for storing the data signals of interest and a packetizer for converting the signals to a plurality of data packets and transmit the data packets to the application software. The application software decodes the transmitted data packets and displays the transactions on a waveform viewer by communicating the information related to the data packets using a plurality of communication protocols.
摘要翻译：本文的各种实施例提供了一种用于使用FPGA提供总线事务监视和调试的方法和系统。该系统包括第一FPGA，第二FPGA，应用软件和用于将第二FPGA与应用软件连接的通信接口。第二个FPGA包括一个用于分接来自第一个FPGA的不同级别的数据信号的监视器RTL，一个基于事务的信号触发器，用于捕获在不同级别的RTL上抽头的信号;一个用于存储感兴趣的数据信号的监视器数据接口和一个打包器用于将信号转换成多个数据分组，并将数据分组发送到应用软件。应用软件通过使用多个通信协议传送与数据分组相关的信息来解码发送的数据分组并在波形观看器上显示交易。

8. 发明申请

US20150276867A1 INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN CHAINS WITH EXCLUSIVE-OR OUTPUTS 有权
标题翻译：具有选择性扫描链的独立或输出的初始化和测试集成电路
公开(公告)号：US20150276867A1
公开(公告)日：2015-10-01
申请号：US14229739
申请日：2014-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G01R31/3177
CPC分类号： G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318516 , G01R31/318519 , G01R31/318558 , G01R31/318561 , G01R31/3187
摘要： Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.
摘要翻译：本发明的实施例提供了一种用于包括多个处理元件的集成电路的扫描测试系统。该系统包括至少一个扫描输入部件和至少一个扫描时钟部件。每个扫描输入组件被配置为向至少两个处理元件提供扫描输入。每个扫描时钟分量被配置为向至少两个处理元件提供扫描时钟信号。该系统还包括至少一个扫描选择部件，用于选择性地启用至少一个处理元件的扫描。每个处理元件被配置为在扫描输入中扫描并且当所述处理元件被扫描启用时扫描出扫描输出。该系统还包括包含多个异或逻辑门的异或树。所述异或树生成表示从所有启用扫描的处理元件扫描的所有扫描输出的奇偶校验值的奇偶校验值。

9. 发明授权

US09041431B1 Partial reconfiguration and in-system debugging 有权
标题翻译：部分重新配置和在系统调试
公开(公告)号：US09041431B1
公开(公告)日：2015-05-26
申请号：US14161460
申请日：2014-01-22
申请人： Altera Corporation
发明人： Alan Louis Herrmann , David W. Mendel
IPC分类号： H03K19/177 , G01R31/28 , H03K19/0175 , G01R31/317 , G01R31/3185
CPC分类号： H03K19/017581 , G01R31/31705 , G01R31/318519 , H03K19/17756
摘要： Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
摘要翻译：嵌入式逻辑在部分可重新配置的可编程逻辑器件（PLD）中实现，从而允许在部分重新配置之后调试实现的逻辑实例。 PLD收到了几个逻辑实例。逻辑的一个实例化在PLD内的可重新配置的逻辑区域中实现。逻辑的实例包括在逻辑的可重新配置区域和PLD内的固定的逻辑区域之间提供恒定接口的端口。端口可以从在可重新配置的逻辑区域内实现的探测点接收信号。端口可以将信号提供给在固定的逻辑区域内实现的信号接口。此外，嵌入式逻辑分析器可以被实现在逻辑的可重新配置区域或逻辑的固定区域中。嵌入式逻辑分析仪从探测点接收信号，并向外部计算系统提供信号可见性。

10. 发明申请

US20150128100A1 CYCLE-ACCURATE REPLAY AND DEBUGGING OF RUNNING FPGA SYSTEMS 有权
标题翻译：循环精确重复和运行FPGA系统的调试
公开(公告)号：US20150128100A1
公开(公告)日：2015-05-07
申请号：US14473058
申请日：2014-08-29
申请人： International Business Machines Corporation
发明人： Daniel Foisy , Sunil K. Shukla
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/318519 , G06F17/5018
摘要： As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system.
摘要翻译：如本文所述，工具记录系统中所有非确定性来源的日志（或跟踪）。在大多数情况下，在系统的所有进入和退出点记录所有转换和确切时间戳就足够了。通过使用该信息，可以在仿真中重新创建硬件系统的周期精确执行。与CHIPSCOPE和SIGNALTAP不同的是，您可以在设计中监视少量信号，该工具可以提供整个系统的可见性。

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