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1. 发明授权

US07509227B2 High-speed digital multiplexer 有权
标题翻译：高速数字多路复用器
公开(公告)号：US07509227B2
公开(公告)日：2009-03-24
申请号：US11671105
申请日：2007-02-05
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G01R31/00 , G01R31/14 , G01R27/28
CPC分类号： G01R31/31926 , G01R31/3191 , G11C29/56
摘要： A high-speed digital multiplexer is disclosed, The multiplexer includes a plurality of input pins for receiving a plurality of digital input signals ad switching circuitry coupled to the input pins. The switching circuitry has respective outputs coupled to a common node and is operative to enable a selected one of the plurality of input pins, The multiplexer further includes a local signal converter having a circuit branch set to a common voltage. The branch is connected to the common node to sense changes in current corresponding to an input signal received by an enabled input pin. An output pin is coupled to the local signal converter, whereby the local signal converter is operative to produce voltage changes at the output corresponding to the sensed current changes.
摘要翻译：公开了一种高速数字多路复用器。多路复用器包括多个输入引脚，用于接收耦合到输入引脚的多个数字输入信号和开关电路。开关电路具有耦合到公共节点的相应输出，并且可操作以使能多个输入引脚中的所选择的输入引脚。多路复用器还包括具有设置为公共电压的电路分支的本地信号转换器。分支连接到公共节点，以检测与由使能输入引脚接收的输入信号相对应的电流变化。输出引脚耦合到本地信号转换器，由此本地信号转换器可操作以在对应于感测的电流变化的输出处产生电压变化。

2. 发明申请

US20080238516A1 Timing interpolator with improved linearity 审中-公开
标题翻译：具有提高线性度的时序插值器
公开(公告)号：US20080238516A1
公开(公告)日：2008-10-02
申请号：US11731339
申请日：2007-03-30
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00052
摘要： A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology.
摘要翻译：可编程定时内插器电路包括低输出阻抗缓冲电路，驱动具有响应于内插器引入的编程延迟而变化的电容的节点。低输出阻抗缓冲电路接收线路延迟信号的子集，并且在缓冲之后，向缓冲电路提供经缓冲的线路延迟信号。缓冲器可以包括彼此耦合的两个源极跟随器级。第一源极跟随器级将接收信号的电平向下移位。第二源极跟随器级将来自第一源极跟随器级的信号的电平向上移位。第一和第二源极跟随器级使用NMOS和PMOS技术来实现。

3. 发明申请

US20130030741A1 METHOD AND SYSTEM FOR MEASURING THE IMPEDANCE OF THE POWER DISTRIBUTION NETWORK IN PROGRAMMABLE LOGIC DEVICE APPLICATIONS 审中-公开
标题翻译：用于测量可编程逻辑器件应用中功率分配网络阻抗的方法和系统
公开(公告)号：US20130030741A1
公开(公告)日：2013-01-31
申请号：US13465024
申请日：2012-05-06
申请人： COSMIN IORGA
发明人： COSMIN IORGA
IPC分类号： G06F19/00
CPC分类号： G01R31/31721 , G01R31/318519
摘要： On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.
摘要翻译：通过仅配置和使用通常可用的逻辑块资源来执行可编程逻辑器件（PLD）（例如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD））的功率分布阻抗频率分布的裸片测量任何现有的可编程逻辑器件，无需内置专用电路。所有的测量都是在可编程逻辑器件内进行的，而无需外部仪器。在表征期间可以使用测量方法来选择去耦电容器或用于对现有系统进行故障排除，之后可重新配置可编程逻辑器件以执行任何其他用户定义的功能。

4. 发明授权

US07222041B2 High-speed digital multiplexer 有权
标题翻译：高速数字多路复用器
公开(公告)号：US07222041B2
公开(公告)日：2007-05-22
申请号：US10010547
申请日：2001-11-08
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G01R31/00
CPC分类号： G01R31/31926 , G01R31/3191 , G11C29/56
摘要： A high-speed digital multiplexer is disclosed. The multiplexer includes a plurality of input pins for receiving a plurality of digital input signals and switching circuitry coupled to the input pins. The switching circuitry has respective outputs coupled to a common node and is operative to enable a selected one of the plurality of input pins. The multiplexer further includes a local signal converter having a circuit branch set to a common voltage. The branch is connected to the common node to sense changes in current corresponding to an input signal received by an enabled input pin. An output pin is coupled to the local signal converter, whereby the local signal converter is operative to produce voltage changes at the output corresponding to the sensed current changes.
摘要翻译：公开了一种高速数字多路复用器。多路复用器包括多个输入引脚，用于接收耦合到输入引脚的多个数字输入信号和开关电路。开关电路具有耦合到公共节点的相应输出，并且可操作以使得所述多个输入引脚中的所选择的输入引脚能够被使能。多路复用器还包括具有设置为公共电压的电路分支的本地信号转换器。分支连接到公共节点，以检测与由使能输入引脚接收的输入信号相对应的电流变化。输出引脚耦合到本地信号转换器，由此本地信号转换器可操作以在对应于感测的电流变化的输出处产生电压变化。

5. 发明授权

US07123075B2 Current mirror compensation using channel length modulation 有权
标题翻译：电流镜补偿采用通道长度调制
公开(公告)号：US07123075B2
公开(公告)日：2006-10-17
申请号：US10671754
申请日：2003-09-26
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G05F1/10
CPC分类号： H03L7/0891 , G05F3/262 , H03L7/0812
摘要： A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor λ1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor λ2. The second channel length modulation factor λ2 is larger than the first channel length modulation factor λ1. As a result, the first programmable current mirror and the second programmable current mirror cooperate to maintain a bias current through the first fanout current mirror stage substantially independent of changes in the supply voltage.
摘要翻译：公开了一种与电流镜电路一起使用的电流补偿电路。电流镜电路具有由驱动第一扇出电流镜级的第一可编程电流镜级限定的电流路径。第一可编程电流镜级包括至少一个具有第一通道长度调制因子λ1的通道长度的晶体管。第一扇出电流镜级连接到电源电压源。电流补偿电路包括耦合到电源电压源的电源电压电流镜，并且具有耦合到电流路径的电流输出。补偿电路还包括与电源电压电流镜串联耦合的第二可编程电流镜，并且包括具有表现出通道长度调制因子λ2的通道长度的至少一个晶体管。第二信道长度调制因子λ2大于第一信道长度调制因子λ1。结果，第一可编程电流镜和第二可编程电流镜协调，以保持基本上与电源电压变化无关的第一扇出电流镜级的偏置电流。

6. 发明授权

US10560075B1 FPGA configured vector network analyzer for measuring the z parameter and s parameter models of the power distribution network in FPGA systems 有权
公开(公告)号：US10560075B1
公开(公告)日：2020-02-11
申请号：US16009203
申请日：2018-06-15
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G01R31/3181 , G01R31/42 , H03K3/011 , H03K3/03 , H03L7/099 , H02J3/24 , G01R31/317 , G01R31/3185 , H02J3/00 , G06Q50/06
摘要： Measurement of power distribution network (PDN) Z-parameters and S-parameters of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks and I/O blocks commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. The measured models include the PDN elements on the PLD die, PLD package, and PCB. The S-parameter and Z-parameter models can be then used in circuit simulation tools to evaluate the power supply noise in the PLD logic core and the timing jitter in the PLD I/O data links.

7. 发明授权

US07885361B2 Method and apparatus for 0/180 degree phase detector 有权
标题翻译： 0/180度相位检测器的方法和装置
公开(公告)号：US07885361B2
公开(公告)日：2011-02-08
申请号：US11311821
申请日：2005-12-19
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： H04L27/00
CPC分类号： H03L7/089 , H04L7/033
摘要： An embodiment of the present invention provides a system for detecting a phase-shifted signal at high frequencies in data and clock recovery circuitry. An up-pulse generator, in one embodiment, provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal leading the reference signal. A down-pulse generator provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal lagging the reference signal.
摘要翻译：本发明的实施例提供一种用于在数据和时钟恢复电路中检测高频相移信号的系统。在一个实施例中，上脉冲发生器在检测到引导参考信号的相移信号时，提供具有超过输入脉冲持续时间的持续时间的输出脉冲。下行脉冲发生器在检测到滞后于参考信号的相移信号时提供具有超过输入脉冲持续时间的持续时间的输出脉冲。

8. 发明申请

US20090167583A1 INTERPOLATION DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：插值数字到模拟转换器
公开(公告)号：US20090167583A1
公开(公告)日：2009-07-02
申请号：US11964254
申请日：2007-12-26
申请人： Cosmin Iorga , Alan Hussey
发明人： Cosmin Iorga , Alan Hussey
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/661 , H03M1/785
摘要： A digital-to-analog converter (DAC) includes coarse interpolation DACs configured to produce a current range based on an input digital signal, and fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs.
摘要翻译：数模转换器（DAC）包括被配置为基于输入数字信号产生电流范围的粗插值DAC和被配置为产生基于输入数字信号的输出电流的精细内插DAC，由粗插值DAC产生的电流范围。

9. 发明授权

US06894552B2 Low-jitter delay cell 有权
标题翻译：低抖动延迟单元
公开(公告)号：US06894552B2
公开(公告)日：2005-05-17
申请号：US10376664
申请日：2003-02-28
申请人： Cosmin Iorga , Alan Hussey , Kuok Ling
发明人： Cosmin Iorga , Alan Hussey , Kuok Ling
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A differential delay cell is disclosed. The delay cell includes a voltage bus and a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output. A current source is disposed at the current node while a differential diode-connected load is disposed between the differential pair and the voltage bus. The differential diode-connected load comprises at least one n-channel MOS transistor configured as a diode.
摘要翻译：公开了一种差分延迟单元。延迟单元包括电压总线和具有耦合以限定电流节点的各个源极端子的MOS晶体管的差分对以及协作以形成差分输出的相应的漏极端子输出。电流源设置在当前节点处，而差分二极管连接的负载设置在差分对和电压总线之间。差分二极管连接的负载包括配置为二极管的至少一个n沟道MOS晶体管。

10. 发明申请

US20050068072A1 Current mirror compensation using channel length modulation 有权
标题翻译：电流镜补偿采用通道长度调制
公开(公告)号：US20050068072A1
公开(公告)日：2005-03-31
申请号：US10671754
申请日：2003-09-26
申请人： Cosmin Iorga
发明人： Cosmin Iorga
IPC分类号： G05F3/24 , G05F3/26 , H03L7/06 , H03L7/081 , H03L7/089
CPC分类号： H03L7/0891 , G05F3/262 , H03L7/0812
摘要： A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor λ1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor λ2. The second channel length modulation factor λ2 is larger than the first channel length modulation factor λ1. As a result, the first programmable current mirror and the second programmable current mirror cooperate to maintain a bias current through the first fanout current mirror stage substantially independent of changes in the supply voltage.
摘要翻译：公开了一种与电流镜电路一起使用的电流补偿电路。电流镜电路具有由驱动第一扇出电流镜级的第一可编程电流镜级限定的电流路径。第一可编程电流镜级包括至少一个具有第一通道长度调制因子λ1的通道长度的晶体管。第一扇出电流镜级连接到电源电压源。电流补偿电路包括耦合到电源电压源的电源电压电流镜，并且具有耦合到电流路径的电流输出。补偿电路还包括与电源电压电流镜串联耦合的第二可编程电流镜，并且包括具有通道长度调制因子λ2的通道长度的至少一个晶体管。第二信道长度调制因子λ2大于第一信道长度调制因子λ1。结果，第一可编程电流镜和第二可编程电流镜协调，以保持基本上与电源电压变化无关的第一扇出电流镜级的偏置电流。

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