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1. 发明申请

US20190079835A1 APPARATUS AND METHOD FOR ENHANCING RELIABILITY OF WATCHDOG CIRCUIT FOR CONTROLLING CENTRAL PROCESSING DEVICE FOR VEHICLE 审中-公开
公开(公告)号：US20190079835A1
公开(公告)日：2019-03-14
申请号：US15822791
申请日：2017-11-27
申请人： Hyundai Motor Company , Kia Motors Corporation
发明人： Chang Seok You , Min Su Kang , Sung Do Kim , Dong Hun Lee
IPC分类号： G06F11/14 , G06F11/07
CPC分类号： G06F11/1497 , G06F11/0739 , G06F11/0757
摘要： An operating method of a vehicle watchdog circuit is provided. The method includes monitoring whether communication with a vehicle controller through a preset protocol is enabled and when a communication fault does not occur by monitoring whether communication is enabled, transmitting an error detection query to the vehicle controller every preset period. A response to the error detection query is received, and an operation of the vehicle controller is monitored, and upon determining that the operation of the vehicle controller is normal, a plurality of preset reset signals are sequentially transmitted to the vehicle controller.

2. 发明申请

US20180307574A1 AUTOMATED TEST GENERATION FOR MULTI-INTERFACE AND MULTI-PLATFORM ENTERPRISE VIRTUALIZATION MANAGEMENT ENVIRONMENT 审中-公开
公开(公告)号：US20180307574A1
公开(公告)日：2018-10-25
申请号：US15492757
申请日：2017-04-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Tariq Hanif , Tin H. To
IPC分类号： G06F11/273 , G06F11/22
CPC分类号： G06F11/3688 , G06F11/1497 , G06F11/1629 , G06F11/1641 , G06F11/165 , G06F11/183 , G06F11/187 , G06F11/2221 , G06F11/2294 , G06F11/3457 , G06F11/3684 , G06F11/3692
摘要： Embodiments for automated testing of a virtualization management system are described. An example computer-implemented method for automated testing of a virtualization management system includes sending, by a test server, a test case to a plurality of instances of the system under test, the test case sent to each instance of the system under test via each interface from a plurality of interfaces supported by the system under test. The method further includes, for each instance of the system under test, performing multi-interface comparison. The comparison includes comparing, by the test server, responses to the test case from each of the interfaces. The method also includes in response to the responses from each of the interfaces being identical, storing the responses in an instance-response file corresponding to the instance. The method also includes reporting, by the test server, an error in response to the responses from each interface not being identical.

3. 发明授权

US09513903B2 Fault-tolerant system and fault-tolerant operating method capable of synthesizing result by at least two calculation modules 有权
标题翻译：能够通过至少两个计算模块合成结果的容错系统和容错操作方法
公开(公告)号：US09513903B2
公开(公告)日：2016-12-06
申请号：US14054643
申请日：2013-10-15
申请人： Industrial Technology Research Institute
发明人： Yung-Chang Chang , Hsing-Chuang Liu , Chih-Jen Yang
IPC分类号： G06F11/16 , G06F9/30 , G06F11/18 , H03K19/003 , G06F11/14
CPC分类号： G06F9/3001 , G06F11/1497 , G06F11/1608 , G06F11/1629 , G06F11/1641 , G06F11/165 , G06F11/183 , G06F11/188 , H03K19/0033
摘要： A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.
摘要翻译：提供了包括计算单元和输出合成器的容错系统。计算单元接收第一环境参数和输入数据，其中所述计算单元还包括第一和第二计算电路。第一计算电路被配置为响应于第一环境参数对输入数据进行计算以产生第一计算结果。第二计算电路与第一计算电路不同，并且被配置为响应于第一环境参数对输入数据进行计算以产生第二计算结果。输出合成器根据控制信号从第一和第二计算结果中选择第一组和第二组，并且顺序地合成第一组位和第二组位，以产生经调整的计算结果。

4. 发明申请

US20160188423A1 SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的同步和顺序检测
公开(公告)号：US20160188423A1
公开(公告)日：2016-06-30
申请号：US15073699
申请日：2016-03-18
申请人： International Business Machines Corporation
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
IPC分类号： G06F11/14 , G11C7/10 , G11C29/52 , G06F11/16
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
摘要翻译：实施例涉及存储器系统中的失步检测和失序检测。一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。存储器控制单元耦合到多个通道。存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。存储器控制单元基于每个通道的偏斜值来调整定时对准。比较每个定时调整的总结输入。基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

5. 发明授权

US09329936B2 Redundant execution for reliability in a super FMA ALU 有权
标题翻译：在超级FMA ALU中冗余执行可靠性
公开(公告)号：US09329936B2
公开(公告)日：2016-05-03
申请号：US13732228
申请日：2012-12-31
申请人： Intel Corporation
发明人： Brian J. Hickman
IPC分类号： G06F9/00 , G06F11/00 , G06F11/14 , G06F11/16
CPC分类号： G06F11/14 , G06F11/1497 , G06F11/1608 , G06F2201/845
摘要： A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the reuse of underutilized hardware to implement spatial redundancy by using detection during the dispatch stage to determine if the operation may be executed by redundant hardware in the ALU. During execution, if determination is made that the correct conditions exists as determined by the redundant execution modes, the SuperFMA ALU performs the operation with redundant execution and compares the results for a match in order to generate a computational result. The method to increase computational reliability by using redundant execution is advantageous because the hardware cost of adding support for redundant execution is low and the complexity of implementation of the disclosed method is minimal due to the reuse of existing hardware.
摘要翻译：一种通过使用SuperFMA ALU通过使用数据路径的不充分部分来增加计算可靠性的系统，处理器和方法。该方法允许利用未充分利用的硬件来重新利用在调度阶段使用检测来实现空间冗余，以确定该操作是否可以由ALU中的冗余硬件执行。在执行期间，如果确定冗余执行模式所确定的正确条件，SuperFMA ALU将执行冗余执行操作，并比较匹配结果以生成计算结果。通过使用冗余执行来增加计算可靠性的方法是有利的，因为对冗余执行的添加支持的硬件成本低，并且由于现有硬件的重用而使所公开的方法的实施的复杂度最小。

6. 发明申请

US20150212905A1 TRANSACTIONAL EXECUTION DIAGNOSTICS USING DIGESTS 有权
公开(公告)号：US20150212905A1
公开(公告)日：2015-07-30
申请号：US14163345
申请日：2014-01-24
申请人： International Business Machines Corporation
发明人： Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/14 , G06F11/07 , G06F9/46
CPC分类号： G06F12/0875 , G06F9/467 , G06F11/0715 , G06F11/0724 , G06F11/0745 , G06F11/0772 , G06F11/1415 , G06F11/1474 , G06F11/1492 , G06F11/1497 , G06F2201/83 , G06F2212/452 , H04L9/3242
摘要： Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional executions is provided. Included is identifying a first indicator, by a computer system, signaling a beginning instruction of a transaction comprising a plurality of instructions; generating, by the computer system, a computed digest based on the execution of at least one of the plurality of instructions; accumulating, by the computer system, a diagnostic data of the transaction based on the execution of the plurality of instructions; identifying, by the computer system, a second indicator associated with the plurality of instructions signaling an ending instruction of the transaction comprising the plurality of instructions; and based on an abort of the transaction, not saving the memory store data of the transaction to memory.

7. 发明授权

US09075621B2 Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution 有权
标题翻译：遇到错误时，或通过在流水线等待队列中重新启动执行时刷新指令，可能会导致错误恢复
公开(公告)号：US09075621B2
公开(公告)日：2015-07-07
申请号：US13336432
申请日：2011-12-23
申请人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
发明人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
IPC分类号： G06F9/38 , G06F11/07 , G06F11/14
CPC分类号： G06F9/3865 , G06F9/3855 , G06F9/3861 , G06F11/0736 , G06F11/0757 , G06F11/1405 , G06F11/1497
摘要： A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
摘要翻译：数据处理装置以流水线执行阶段的顺序执行指令。错误检测单元对与执行指令相关联的信号进行两次采样，并且如果样本不同则产生误差信号。异常存储单元维护与发出到执行流水线的指令相对应的条目的年龄排序列表，并且可以标记条目以显示是否已经与该指令相关联地生成了错误信号。定时器单元响应于产生误差信号以启动预定时间段的定时。如果列表中的最旧的等待条目具有与其相关联地存储的所述错误标记，则错误恢复单元启动软管道冲洗过程，并且如果所述预定时间段过去则启动硬管道冲洗过程，所述硬冲洗程序包括将所述流水线重置为预定状态。

8. 发明授权

US09063907B2 Comparison for redundant threads 有权
标题翻译：冗余线程的比较
公开(公告)号：US09063907B2
公开(公告)日：2015-06-23
申请号：US13796304
申请日：2013-03-12
申请人： Renesas Electronics Corporation
发明人： Hiromichi Yamada , Nobuyasu Kanekawa , Tsutomu Yamada , Kesami Hagiwara
IPC分类号： G06F11/00 , G06F11/20 , G06F9/48 , G06F11/14 , G06F21/56 , G06F11/16
CPC分类号： G06F11/2041 , G06F9/4881 , G06F11/1492 , G06F11/1497 , G06F11/1641 , G06F11/1691 , G06F21/566
摘要： The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.
摘要翻译：本发明提供了一种半导体集成电路器件，其在抑制性能劣化的同时实现故障的检测。在与时钟同步地切换的同时执行多个线程的半导体集成电路装置中，为各线程提供用于执行线程的寄存器。彼此独立的程序和与线程相同的程序在切换时执行。在通过多个线程执行相同的程序的情况下，提供用于比较使用与线程相对应地提供的寄存器的执行结果的比较电路。

9. 发明授权

US09043640B1 System and method for event-driven live migration of multi-process applications 有权
公开(公告)号：US09043640B1
公开(公告)日：2015-05-26
申请号：US12957637
申请日：2010-12-01
申请人： Allan Havemose
发明人： Allan Havemose
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G06F11/1497 , G06F11/1438 , G06F11/1482 , G06F11/1683 , G06F11/203 , G06F11/2041 , G06F11/2046 , G06F11/2097 , G06F2201/805 , G06F2201/82 , G06F2201/825
摘要： A system, method, and computer readable medium for asynchronous live migration of applications between two or more servers. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. Asynchronous live migration is provided through a combination of process replication, logging, barrier synchronization, checkpointing, reliable messaging and message playback. The live migration is transparent to the application and requires no modification to the application, operating system, networking stack or libraries.

10. 发明授权

US09032190B2 Recovering from an error in a fault tolerant computer system 有权
标题翻译：从容错计算机系统中的错误中恢复
公开(公告)号：US09032190B2
公开(公告)日：2015-05-12
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38 , G06F11/14 , G06F11/16
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译：并行执行前导线程和后退线程。假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。

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