专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10839933B2 Memory devices having a read function of data stored in a plurality of reference cells 有权
公开(公告)号：US10839933B2
公开(公告)日：2020-11-17
申请号：US16445149
申请日：2019-06-18
申请人： MICRON TECHNOLOGY, INC.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C29/52 , G11C11/16 , G06F11/10 , G06F11/08 , G06F11/16 , G06F11/20 , G11C29/04 , G11C13/00
CPC分类号： G11C29/52 , G06F11/08 , G06F11/1048 , G06F11/1068 , G11C11/1673 , G06F11/16 , G06F11/167 , G06F11/1608 , G06F11/1612 , G06F11/1658 , G06F11/1662 , G06F11/1666 , G06F11/20 , G11C11/16 , G11C13/00 , G11C29/04 , G11C2029/0409 , G11C2029/0411
摘要： A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.

2. 发明授权

US09798599B2 Apparatus for monitoring operating conditions of a logic circuit to determine failure of one or more latches 有权
公开(公告)号：US09798599B2
公开(公告)日：2017-10-24
申请号：US14631128
申请日：2015-02-25
申请人： STMicroelectronics International N.V.
发明人： Chittoor Parthasarathy , Abhishek Jain
IPC分类号： G06F11/00 , G06F11/14 , G06F11/30 , G06F11/07 , H03K3/037 , G06F11/16
CPC分类号： G06F11/0751 , G06F11/1608 , H03K3/0375
摘要： An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

3. 发明授权

US09148670B2 Multi-core decompression of block coded video data 有权
标题翻译：块编码视频数据的多核解压缩
公开(公告)号：US09148670B2
公开(公告)日：2015-09-29
申请号：US13306983
申请日：2011-11-30
申请人： Atul Kumar , Ankush Jain , Rituja Srivastava
发明人： Atul Kumar , Ankush Jain , Rituja Srivastava
IPC分类号： H04N19/436 , H04N19/44 , H04N19/61 , H04N19/65 , H04N19/66 , G06F11/16 , G06F11/20
CPC分类号： H04N19/436 , G06F11/1608 , G06F11/1629 , G06F11/1658 , G06F11/1687 , G06F11/202 , H04N19/44 , H04N19/61 , H04N19/65 , H04N19/66
摘要： Apparatus for and a method of decompression of block coded video data in a multi-core processor. The processor cores decode respective coded groups of blocks of video data independently, in parallel and deblock respective decoded groups of blocks of video data independently and in parallel with the decode operations and with other deblock operations.
摘要翻译：用于在多核处理器中对块编码视频数据进行解压缩的装置和方法。处理器核心独立地并行地解码视频数据块的各个编码组，并且独立地并且与解码操作和其它解块操作并行解码各个解码的视频数据块组。

4. 发明授权

US09109936B2 Measuring device electronics for a measuring device as well as measuring device formed therewith 有权
标题翻译：用于测量装置的测量装置电子装置以及由其形成的测量装置
公开(公告)号：US09109936B2
公开(公告)日：2015-08-18
申请号：US13484444
申请日：2012-05-31
申请人： Wolfgang Drahm , Gernot Engstler , Hans Pohl , Christian Matt , Robert Lalla , Matthias Brudermann
发明人： Wolfgang Drahm , Gernot Engstler , Hans Pohl , Christian Matt , Robert Lalla , Matthias Brudermann
IPC分类号： G06F1/26 , G01F1/84 , G06F11/16
CPC分类号： G01F1/8431 , G01F1/8436 , G01F1/8477 , G06F11/1604 , G06F11/1608
摘要： A measuring device electronics comprises a processor and two clock signal generators. One clock signal generator serves for producing a working clock signal, and also for producing a reference clock signal which is dependant on the working clock signal. The other clock signal generator, serves for producing a second reference clock signal, which is independent of the working clock signal. Based on the two independent reference clock signals, a frequency difference, can, to the extent that such is present, be ascertained during operation of the measuring device electronics or of the measuring device formed therewith. The frequency difference, represents a difference between the instantaneous clocking frequency of the first reference clock signal and the instantaneous clocking frequency of the second reference clock signal, and, in this respect, represents a measure for a deviation of an instantaneous clocking frequency, from the nominally predetermined clocking frequency, of the working clock signal.
摘要翻译：测量装置电子器件包括处理器和两个时钟信号发生器。一个时钟信号发生器用于产生工作时钟信号，并且还用于产生取决于工作时钟信号的参考时钟信号。另一个时钟信号发生器用于产生独立于工作时钟信号的第二参考时钟信号。基于两个独立的参考时钟信号，可以在测量装置电子装置或由此形成的测量装置的操作期间确定频率差，在这样的程度上。频率差表示第一参考时钟信号的瞬时时钟频率和第二参考时钟信号的瞬时时钟频率之间的差，并且在这方面表示瞬时时钟频率与名义上预定的工作时钟信号的时钟频率。

5. 发明授权

US09009545B2 Pulsed-latch based razor with 1-cycle error recovery scheme 有权
标题翻译：基于脉冲闩锁的剃刀与1周期错误恢复方案
公开(公告)号：US09009545B2
公开(公告)日：2015-04-14
申请号：US13918587
申请日：2013-06-14
申请人： International Business Machines Corporation
发明人： Jae-Joon Kim , Yu-Shiang Lin , Insup Shin
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/2215 , G06F1/04 , G06F1/10 , G06F11/1402 , G06F11/1407 , G06F11/1415 , G06F11/1604 , G06F11/1608
摘要： Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.
摘要翻译：用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

6. 发明授权

US08996937B2 Apparatus for monitoring operating conditions of a logic circuit 有权
标题翻译：用于监视逻辑电路的操作条件的装置
公开(公告)号：US08996937B2
公开(公告)日：2015-03-31
申请号：US13489034
申请日：2012-06-05
申请人： Abhishek Jain , Chittoor Parthasarathy
发明人： Abhishek Jain , Chittoor Parthasarathy
IPC分类号： G06F11/16
CPC分类号： G06F11/0751 , G06F11/1608 , H03K3/0375
摘要： An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
摘要翻译：电路的实施例包括数据锁存器和多个级联锁存器，其中多个级联锁存器中的第一个锁存器被配置为从数据锁存器接收第一信号，并且每个后续级联锁存器被配置为接收数据锁存器的数据输出信号一个先前的级联锁存器和一个错误检测电路，配置成接收相应的数据输出信号，并在此基础上检测级联锁存器工作中的错误。

7. 发明申请

US20140163907A1 SYSTEMS AND METHODS FOR FAULT DETECTION 审中-公开
标题翻译：用于故障检测的系统和方法
公开(公告)号：US20140163907A1
公开(公告)日：2014-06-12
申请号：US13709928
申请日：2012-12-10
申请人： GENERAL ELECTRIC COMPANY
发明人： Daniel Milton Alley , Michael G. Wise , Alan Mathason , Fred Henry Boettner , Stephen Emerson Douthit , Richard Reed
IPC分类号： G01R31/00 , G06F15/00
CPC分类号： G01R31/00 , G05B9/02 , G05B9/03 , G06F11/1608 , G06F11/1625 , G06F11/186 , G06F11/188 , G06F15/00 , G06F2201/81
摘要： Systems, methods, and computer-readable media for fault detection are disclosed. At least one controller may identify a plurality of values where each value corresponds to a monitored parameter or a measured parameter. The at least one controller may determine a respective deviation between each of the plurality of values and an expected value, and may further determine whether at least one of the respective deviations exceeds a threshold. Upon a determination that at least one of the respective deviations exceeds the threshold, a fault may be detected. Each of the plurality of values may be associated with a respective device that monitors or measures the value. A detected fault may be associated with the device that monitors or measures the value determined to deviate from the expected value by more than the threshold.
摘要翻译：公开了用于故障检测的系统，方法和计算机可读介质。至少一个控制器可以标识多个值，其中每个值对应于被监视的参数或测量的参数。所述至少一个控制器可以确定所述多个值中的每一个与预期值之间的相应偏差，并且还可以确定各个偏差中的至少一个是否超过阈值。在确定各个偏差中的至少一个超过阈值时，可以检测到故障。多个值中的每一个可以与监视或测量该值的相应设备相关联。检测到的故障可以与监视或测量所确定的偏离预期值大于阈值的设备相关联。

8. 发明授权

US08156251B1 Advanced logic system 有权
标题翻译：先进的逻辑系统
公开(公告)号：US08156251B1
公开(公告)日：2012-04-10
申请号：US12914724
申请日：2010-10-28
申请人： Steen Ditlev Sorensen , Sten Sogaard
发明人： Steen Ditlev Sorensen , Sten Sogaard
IPC分类号： G06F3/00
CPC分类号： G06F11/1641 , G05B23/0291 , G05B2219/24054 , G05B2219/34334 , G06F11/0796 , G06F11/1004 , G06F11/1608 , G06F11/1616 , G06F11/2007 , G06F11/2015 , G06F11/27 , H04L12/40013 , H04L12/40176
摘要： The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.
摘要翻译：高级逻辑系统（ALS）是一个基于硬件平台而不是基于软件的微处理器系统的完整的控制系统架构。通过在中央控制单元中实现FPGA，与其他PLC型控制系统架构显着不同。使用标准FPGA逻辑电路而不是基于软件的微处理器，消除基于软件的微处理器系统的问题，例如软件共模故障。它提供了一个高度可靠的系统，适用于安全关键控制系统，包括核电站保护系统。系统采样过程输入，提供数字总线通信，应用控制逻辑功能，并提供受控输出。该架构结合了多个级别的高级功能，如诊断，可测试性和冗余度。它还提供了故障检测，隔离和缓解方面的显着改进，以实现最高级别的完整性和可靠性。

9. 发明申请

US20110093737A1 Error recovery within processing stages of an integrated circuit 有权
公开(公告)号：US20110093737A1
公开(公告)日：2011-04-21
申请号：US12923911
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/07
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

10. 发明申请

US20100131741A1 MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT 有权
标题翻译：具有检测加工结果的多核微型计算机
公开(公告)号：US20100131741A1
公开(公告)日：2010-05-27
申请号：US12610422
申请日：2009-11-02
申请人： Hiromichi YAMADA , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
发明人： Hiromichi YAMADA , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
IPC分类号： G06F9/30 , G06F9/44 , G06F9/38
CPC分类号： G06F11/1608 , G06F11/004 , G06F11/1641 , G06F11/1687 , G06F2201/83 , G06F2201/845
摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.
摘要翻译：一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式