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1. 发明申请

US20150146475A1 MEMORY SENSE AMPLIFIER WITH MULTIPLE MODES OF OPERATION 有权
标题翻译：具有多种操作模式的记忆感应放大器
公开(公告)号：US20150146475A1
公开(公告)日：2015-05-28
申请号：US14092395
申请日：2013-11-27
申请人： Bharan GIRIDHAR , David Theodore BLAAUW , Dennis Michael SYLVESTER
发明人： Bharan GIRIDHAR , David Theodore BLAAUW , Dennis Michael SYLVESTER
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C7/08 , G11C11/419
摘要： Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.
摘要翻译：存储器电路包括一个6位元单元6的阵列，其中位单元的列通过连接到相应读出放大器电路10的位线对8耦合在一起。读出放大器电路包括反相器对12,14和控制电路，其被配置为控制读出放大器电路以包括偏移补偿模式，放大模式和锁存模式的多种模式操作。

2. 发明授权

US08650470B2 Error recovery within integrated circuit 有权
标题翻译：集成电路内的错误恢复
公开(公告)号：US08650470B2
公开(公告)日：2014-02-11
申请号：US12926084
申请日：2010-10-25
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/00 , G06F11/0706 , G06F11/0736 , G06F11/0754 , G06F11/0757 , G06F11/079 , G06F11/1402 , G06F11/1604
摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
摘要翻译：集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

3. 发明授权

US08407537B2 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US08407537B2
公开(公告)日：2013-03-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F1/08 , G06F11/30
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

4. 发明授权

US08335122B2 Cache memory system for a data processing apparatus 有权
标题翻译：用于数据处理装置的高速缓冲存储器系统
公开(公告)号：US08335122B2
公开(公告)日：2012-12-18
申请号：US12292148
申请日：2008-11-12
申请人： Ronald George Dreslinski, Jr. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
发明人： Ronald George Dreslinski, Jr. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
IPC分类号： G11C5/14
CPC分类号： G06F12/0897 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
摘要翻译：提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访问请求而耦合到高速缓冲存储器的高速缓存控制器。高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。还提供了相应的数据处理方法。

5. 发明授权

US08185812B2 Single event upset error detection within an integrated circuit 有权
标题翻译：集成电路内的单事件镦粗错误检测
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
申请人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
发明人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译：集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

6. 发明授权

US08107290B2 Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device 有权
标题翻译：存储单元结构，采用这种存储单元结构的存储器件，以及具有这种存储器件的集成电路
公开(公告)号：US08107290B2
公开(公告)日：2012-01-31
申请号：US12078547
申请日：2008-04-01
申请人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
发明人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416 , G11C16/0441 , G11C2216/10 , H01L27/0629 , H01L27/0805 , H01L27/11521 , H01L27/11526 , H01L27/11558 , H01L28/40
摘要： A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.
摘要翻译：用于存储器件的存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。隧道电容器连接到浮动栅极节点并具有第一编程端子，耦合电容器堆叠连接到浮动栅极节点并具有第二编程端子。耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。这样的存储单元结构在面积上是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了常规EEPROM和闪存器件的生产中涉及的一些复杂性。

7. 发明申请

US20110126051A1 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US20110126051A1
公开(公告)日：2011-05-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/267
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

8. 发明授权

US07864562B2 Integrated circuit memory access mechanisms 有权
标题翻译：集成电路存储器访问机制
公开(公告)号：US07864562B2
公开(公告)日：2011-01-04
申请号：US12379820
申请日：2009-03-02
申请人： Gregory Kengho Chen , Dennis Michael Sylvester , David Theodore Blaauw
发明人： Gregory Kengho Chen , Dennis Michael Sylvester , David Theodore Blaauw
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.
摘要翻译：集成电路存储器内的存储单元36具有耦合到第一传输门38和第二传输门40的访问控制器32.在对存储单元38的写访问期间，第一传输门38和第二传输门 40打开。在读取访问期间，打开第一传递门38并关闭第二传递门40。读写操作中的这种不对称允许形成存储单元36的门的不对称性，从而允许改变增加读稳健性和写鲁棒性。不同栅极的设计参数中的不对称可以采取改变栅极长度，栅极宽度和阈值电压的形式，以便改变不同栅极的电导以适应其在存储单元36内的各自的作用由分离的字线提供的非对称方式驱动读操作和写操作。

9. 发明授权

US07278080B2 Error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误检测和恢复
公开(公告)号：US07278080B2
公开(公告)日：2007-10-02
申请号：US10392382
申请日：2003-03-20
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a maimer that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便在增加整体性能的情况下保持有限的非零错误率。

10. 发明授权

US07162661B2 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US07162661B2
公开(公告)日：2007-01-09
申请号：US10779805
申请日：2004-02-18
申请人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
发明人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
IPC分类号： G06F11/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

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