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1. 发明公开

US20230418774A1 INTEGRATED CIRCUIT, CHIP, AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20230418774A1
公开(公告)日：2023-12-28
申请号：US18467379
申请日：2023-09-14
申请人： Huawei Technologies Co., Ltd.
发明人： Yan Zhao , Ke Zhang , Yu Liang , Jian Zhang , Nan Li
IPC分类号： G06F13/368 , G06F13/16
CPC分类号： G06F13/368 , G06F13/1668
摘要： This disclosure provides an integrated circuit, a chip, and an electronic device. The chip includes D dice, where D is a positive integer greater than or equal to 2, the D dice include a first die and a second die, and the first die and the second die are rotationally symmetrical.

2. 发明申请

US20180336149A1 COORDINATED EVENT SEQUENCING 审中-公开
公开(公告)号：US20180336149A1
公开(公告)日：2018-11-22
申请号：US15727561
申请日：2017-10-06
申请人： Linear Technology Holding LLC
发明人： Michael David Petersen , Raymond Allen Stevens
IPC分类号： G06F13/362 , G06F13/42 , G06F11/07 , G06F1/32
CPC分类号： G06F13/362 , G06F1/32 , G06F11/0706 , G06F11/0745 , G06F11/0757 , G06F11/0766 , G06F13/368 , G06F13/4282
摘要： Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

3. 发明授权

US09304959B2 Method of optimizing the width of transaction ID for an interconnecting bus 有权
标题翻译：优化互连总线的交易ID宽度的方法
公开(公告)号：US09304959B2
公开(公告)日：2016-04-05
申请号：US13965226
申请日：2013-08-13
申请人： Ying-Ze Liao , Pei Yu , Yung-Sheng Fang
发明人： Ying-Ze Liao , Pei Yu , Yung-Sheng Fang
IPC分类号： G06F13/368
CPC分类号： G06F13/368
摘要： The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.
摘要翻译：本发明公开了一种在总线互连设计中产生交易ID的方法。可以通过计算从所有主机到从机的所有可能的事务来导出每个从机的编码表，以便确定从机在互连总线设计中接收到的事务ID的最小宽度，从而避免互连中的路由拥塞总线。

4. 发明授权

US09122802B2 Interconnect, bus system with interconnect and bus system operating method 有权
标题翻译：互联，总线系统与互连和总线系统操作方法
公开(公告)号：US09122802B2
公开(公告)日：2015-09-01
申请号：US14217536
申请日：2014-03-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Joon-Woo Cho , Jong Ho Roh , Jae Geun Yun , Sung-Min Hong
IPC分类号： G06F13/00 , G06F13/368 , G06F13/40 , G06F13/28 , G06F15/78 , G06F12/06
CPC分类号： G06F13/368 , G06F12/0607 , G06F13/4022
摘要： Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.
摘要翻译：提供互连，具有互连的总线系统和总线系统操作方法。总线系统包括主站，主站的从站访问和互连。响应于由主机提供的主地址中标识的选择位，互连将主机与从机连接。

5. 发明申请

US20140317323A1 Method and Apparatus for Arbitration with Multiple Source Paths 有权
标题翻译：多源路径仲裁的方法和装置
公开(公告)号：US20140317323A1
公开(公告)日：2014-10-23
申请号：US13868313
申请日：2013-04-23
申请人： APPLE INC.
发明人： Benjamin K. Dodge , Deniz Balkan , Gurjeet S. Saund , Munetoshi Fukami
IPC分类号： G06F13/368
CPC分类号： G06F13/368 , G06F13/16
摘要： A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.
摘要翻译：一种用于仲裁的方法和装置。在一个实施例中，网络中的一个点包括第一和第二仲裁器。与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。每个事务是具有相应优先级的多个不同事务类型之一。耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易的类型。测量电路可以更新与获胜交易的类型相关联的多个信用。可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。

6. 发明授权

US08775700B2 Issuing requests to a fabric 有权
标题翻译：向织物发出请求
公开(公告)号：US08775700B2
公开(公告)日：2014-07-08
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求源代理程序在第一个时钟周期。然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。描述和要求保护其他实施例。

7. 发明申请

US20120059959A1 Method for Assigning Addresses to Nodes of a Bus System, and Installation 审中-公开
标题翻译：分配地址到总线系统节点的方法和安装
公开(公告)号：US20120059959A1
公开(公告)日：2012-03-08
申请号：US13221436
申请日：2011-08-30
申请人： Olaf Simon
发明人： Olaf Simon
IPC分类号： G06F13/00
CPC分类号： G06F13/404 , G06F12/0661 , G06F13/368 , G06F13/385 , G06F13/4265 , G06F2213/0052 , H04L29/12254 , H04L61/2038
摘要： A method for assigning addresses to nodes of a bus system, and installation,bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.
摘要翻译：一种用于向总线系统的节点分配地址的方法，以及安装总线节点具有相同的传送地址，其中（i）分配实体，特别是中央计算机，启动计算机或总线节点向传送信息发送信息（ii）信息包括第一地址，（iii）执行其效果由第一总线节点检测到的动作，（iv）第一总线节点接受第一地址，（v）第一地址总线节点向分配实体发送响应，（vi）重复步骤（i）至（v），每次都有另一个总线节点的另一个地址。

8. 发明授权

US07809861B1 System memory map decoder logic 有权
标题翻译：系统内存映射解码逻辑
公开(公告)号：US07809861B1
公开(公告)日：2010-10-05
申请号：US10856539
申请日：2004-05-27
申请人： Jeffrey Orion Pritchard , Peter Hutkins
发明人： Jeffrey Orion Pritchard , Peter Hutkins
IPC分类号： G06F13/14
CPC分类号： G06F13/4265 , G06F13/368
摘要： Methods and apparatus are provided optimizing system memory map decoder logic. A system is configured with multiple master and slave components. Using information known about the system configuration, optimized decoder logic can be configured. Critical path delay and system resource usage are reduced by optimizing decoder logic.
摘要翻译：提供了优化系统存储器映射解码器逻辑的方法和装置。系统配置有多个主从组件。使用有关系统配置的信息，可以配置优化的解码器逻辑。通过优化解码器逻辑来减少关键路径延迟和系统资源使用。

9. 发明授权

US07698485B2 Round-robin bus protocol 有权
标题翻译：循环总线协议
公开(公告)号：US07698485B2
公开(公告)日：2010-04-13
申请号：US12025462
申请日：2008-02-04
申请人： Yasser Ahmed
发明人： Yasser Ahmed
IPC分类号： G06F13/00
CPC分类号： G06F13/368
摘要： A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.
摘要翻译：提供了包括一个或多个数据线和一个或多个控制线的低等待时间的对等TDM总线。连接的设备按照总线地址顺序访问总线。在设备访问期间，如果设备具有要发送的数据，则设备将其地址放置在数据线上，在总线上断言START信号，并继续向总线上的其他设备发送数据。当数据传输完成时，器件在总线上断言END信号，从而将总线的控制按顺序传送到下一个器件。如果设备没有要发送的数据，则设备只需将其地址放置在数据线上，断言START信号，并断言END信号，并且控制直接传递到下一个设备。以这种方式，每个设备都有机会在总线上传输。

10. 发明申请

US20090070507A1 Back-Off Timing Mechanism 失效
标题翻译：后退时机机制
公开(公告)号：US20090070507A1
公开(公告)日：2009-03-12
申请号：US11853898
申请日：2007-09-12
申请人： Shigehiro Asano , Tsutomu Ishii
发明人： Shigehiro Asano , Tsutomu Ishii
IPC分类号： G06F13/00
CPC分类号： G06F13/368
摘要： Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.
摘要翻译：用于通过分割事务总线实现从主设备发送到从设备的命令重试的退避时序的系统和方法。一个实施例包括具有用于存储每个未决命令和相关信息的条目的缓冲器，包括命令的重试次数和静态伪随机定时器到期值。根据与对应于条目的命令的重试次数相关联的掩码，将每个条目的定时器到期值与运行计数器进行比较。当两个值的未屏蔽位匹配时，将重试该命令。在一个实施例中，用于存储重试次数和定时器到期值的缓冲器条目的相同部分交替地用于存储用确认响应接收的从生产标签。

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