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1. 发明授权

US09602464B2 Apparatus, system and method for allocating identifiers to components of a control system 有权
公开(公告)号：US09602464B2
公开(公告)日：2017-03-21
申请号：US14569521
申请日：2014-12-12
申请人： Werner Hein , Martin Polak , David Loesch
发明人： Werner Hein , Martin Polak , David Loesch
IPC分类号： H04L29/12 , H04L12/403 , G06F13/42 , H04W8/26
CPC分类号： H04L61/2061 , G06F13/42 , G06F2213/0052 , H04B1/406 , H04L12/403 , H04L61/2038 , H04L61/2046 , H04W8/26
摘要： Techniques and mechanisms to enable addressing of components accessed via a control interface. In an embodiment, a plurality of identifiers is logically split into first and second pools. The first pool is available for assigning to allow addressing of components while such components are active with respect to some functionality. The second pool is available for assigning to allow addressing of components while such components are passive with respect to some functionality. In another embodiment, different respective identifiers of the first pool pool are assigned each of first one or more of the plurality of components, and a respective identifier of the second pool is assigned to each of second one or more of the plurality of components. Any two of the second one or more components that have the same address default are assigned different respective identifiers of the second pool.

2. 发明授权

US09588926B2 Input/output swtiching module interface identification in a multi-server chassis 有权
标题翻译：多服务器机箱中的输入/输出交换模块接口标识
公开(公告)号：US09588926B2
公开(公告)日：2017-03-07
申请号：US15056712
申请日：2016-02-29
申请人： Dell Products L.P.
发明人： Ramesh Balaji Subramanian
IPC分类号： G06F13/40 , G06F13/366 , G06F3/06
CPC分类号： G06F13/4022 , G06F3/0689 , G06F13/366 , G06F2213/0052
摘要： An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.
摘要翻译：接口识别系统包括包括多个IHS时隙和多个输入/输出（I / O）切换模块时隙的IHS机箱。连接平面提供多个IHS时隙和多个I / O切换模块时隙之间的互连。 I / O切换模块包括多个接口。 I / O切换模块可以耦合到第一I / O切换模块插槽，并且作为响应，检索关于第一I / O切换模块插槽的第一I / O切换模块插槽信息，检索关于位于多个IHS时隙，其通过连接平面与第一I / O切换模块插槽互连，并且使用第一I / O切换模块时隙信息和IHS信息来识别I / O切换上的多个接口中的每一个模块通过IHS和第一个I / O切换模块插槽耦合到IHS。

3. 发明申请

US20160179729A1 INPUT/OUTPUT SWTICHING MODULE INTERFACE IDENTIFICATION IN A MULTI-SERVER CHASSIS 有权
标题翻译：多服务器机箱中的输入/输出切换模块接口识别
公开(公告)号：US20160179729A1
公开(公告)日：2016-06-23
申请号：US15056712
申请日：2016-02-29
申请人： Dell Products L.P.
发明人： Ramesh Balaji Subramanian
IPC分类号： G06F13/40 , G06F13/366
CPC分类号： G06F13/4022 , G06F3/0689 , G06F13/366 , G06F2213/0052
摘要： An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.
摘要翻译：接口识别系统包括包括多个IHS时隙和多个输入/输出（I / O）切换模块时隙的IHS机箱。连接平面提供多个IHS时隙和多个I / O切换模块时隙之间的互连。 I / O切换模块包括多个接口。 I / O切换模块可以耦合到第一I / O切换模块插槽，并且作为响应，检索关于第一I / O切换模块插槽的第一I / O切换模块插槽信息，检索关于位于多个IHS时隙，其通过连接平面与第一I / O切换模块插槽互连，并且使用第一I / O切换模块时隙信息和IHS信息来识别I / O切换上的多个接口中的每一个模块通过IHS和第一个I / O切换模块插槽耦合到IHS。

4. 发明申请

US20150378952A1 METHOD AND APPARATUS OF USB 3.1 RETIMER PRESENCE DETECT AND INDEX 有权
标题翻译： USB 3.1退出存在检测和索引的方法和装置
公开(公告)号：US20150378952A1
公开(公告)日：2015-12-31
申请号：US14317874
申请日：2014-06-27
申请人： Intel Corporation
发明人： Huimin Chen , Howard L. Heck
IPC分类号： G06F13/42
CPC分类号： G06F13/423 , G05B2219/25181 , G06F13/4045 , G06F13/4256 , G06F2213/0052 , H04B3/58 , H04B10/29 , H04B2203/5479 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.
摘要翻译：本文描述了重新定时器存在检测的装置。该装置包括至少一个重定时器，其中算法是使得至少一个重定时器通过在链路初始化期间断言存在消息的位来通知其存在。至少一个重定时器可以声明一个索引并且可以通过索引访问。

5. 发明授权

US08943256B1 Serial data intermediary device, and related systems and methods 有权
标题翻译：串行数据中介设备及相关系统及方法
公开(公告)号：US08943256B1
公开(公告)日：2015-01-27
申请号：US14133359
申请日：2013-12-18
申请人： Cypress Semiconductor Corporation
发明人： Gregory J. Landry , Edward L. Grivna
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4004 , G06F13/385 , G06F13/404 , G06F13/4045 , G06F13/4054 , G06F13/4282 , G06F2213/0016 , G06F2213/0052
摘要： An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.
摘要翻译：集成电路（IC）装置可以包括电耦合到IC器件的第一物理连接并被配置为响应在第一物理连接处接收的通信信号的串行通信第一接口（I / F）电路; 至少一个串行通信第二接口（I / F）电路，其电耦合到所述IC设备的第二物理连接，并且被配置为允许通过所述第二物理连接进行数据交易; 以及中继器电路，被配置为绕过所述第一I / F电路并且使串行通信信号能够从所述第一物理连接发送到所述第二物理连接。还公开了包括这种IC器件和相关方法的系统。

6. 发明申请

US20140281111A1 INPUT/OUTPUT SWTICHING MODULE INTERFACE IDENTIFICATION IN A MULTI-SERVER CHASSIS 有权
标题翻译：多服务器机箱中的输入/输出切换模块接口识别
公开(公告)号：US20140281111A1
公开(公告)日：2014-09-18
申请号：US13899290
申请日：2013-05-21
申请人： Dell Products L.P.
发明人： Ramesh Balaji Subramanian
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F3/0689 , G06F13/366 , G06F2213/0052
摘要： An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.
摘要翻译：接口识别系统包括包括多个IHS时隙和多个输入/输出（I / O）切换模块时隙的IHS机箱。连接平面提供多个IHS时隙和多个I / O切换模块时隙之间的互连。 I / O切换模块包括多个接口。 I / O切换模块可以耦合到第一I / O切换模块插槽，并且作为响应，检索关于第一I / O切换模块插槽的第一I / O切换模块插槽信息，检索关于位于多个IHS时隙，其通过连接平面与第一I / O切换模块插槽互连，并且使用第一I / O切换模块时隙信息和IHS信息来识别I / O切换上的多个接口中的每一个模块通过IHS和第一个I / O切换模块插槽耦合到IHS。

7. 发明授权

US08626976B2 Method and apparatus for performing a host enumeration process 有权
标题翻译：用于执行主机枚举过程的方法和装置
公开(公告)号：US08626976B2
公开(公告)日：2014-01-07
申请号：US12919050
申请日：2008-02-26
申请人： David L. Matthews , Hubert E. Brinkmann , Barry S. Basile , Paul V. Brownell , Kevin G Depew
发明人： David L. Matthews , Hubert E. Brinkmann , Barry S. Basile , Paul V. Brownell , Kevin G Depew
IPC分类号： G06F13/20 , G06F13/36 , G06F3/00 , G06F9/00 , G06F13/00 , G06F13/38 , G06F13/40 , G06F9/44 , H04L29/08 , H04L12/24
CPC分类号： G06F13/385 , G06F9/4401 , G06F9/4411 , G06F13/4022 , G06F13/4027 , G06F2213/0052 , H04L29/08144 , H04L41/0213
摘要： A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.
摘要翻译：一种用于主机枚举过程的方法和装置。该方法的一个实施例提供一点以向主机指示枚举过程是应该开始还是继续。当共享资源处理已经成功完成时，可以设置该位，或者如果从共享资源处理开始以来已经过了太多时间，则可以设置该位，或者如果在共享资源处理之前经过了太多时间启动资源处理，或者如果共享资源处理尚未成功执行，则可以设置该位，或者如果端口打开并且不必执行共享资源处理，则可以设置该位。

8. 发明申请

US20130346635A1 Assigning Addresses To Devices On An Interconnect 有权
标题翻译：在互连上为设备分配地址
公开(公告)号：US20130346635A1
公开(公告)日：2013-12-26
申请号：US13532978
申请日：2012-06-26
申请人： Jeff Morriss , David J. Harriman
发明人： Jeff Morriss , David J. Harriman
IPC分类号： G06F3/00
CPC分类号： G06F13/00 , G06F9/5011 , G06F9/5027 , G06F13/4282 , G06F21/445 , G06F21/73 , G06F2213/0042 , G06F2213/0052 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes an apparatus having a random number generator to generate a random number responsive to a first command from a host controller and a logic to generate a device identifier for the apparatus. The apparatus can provide a reply to the host controller including the random number responsive to an identification request from the host controller corresponding to the device identifier. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有随机数发生器的装置，用于响应于来自主机控制器的第一命令产生随机数，以及生成用于该装置的设备标识符的逻辑。该装置可以向主机控制器提供响应于来自主机控制器的对应于设备标识符的识别请求的随机数的回复。描述和要求保护其他实施例。

9. 发明申请

US20130132626A1 PIN SELECTABLE I2C SLAVE ADDRESSES 有权
标题翻译： PIN可选I2C从地址
公开(公告)号：US20130132626A1
公开(公告)日：2013-05-23
申请号：US13679465
申请日：2012-11-16
申请人： Igor Furlan
发明人： Igor Furlan
IPC分类号： G06F13/20
CPC分类号： G06F13/36 , G06F12/0669 , G06F13/385 , G06F2213/0016 , G06F2213/0052 , Y02D10/14 , Y02D10/151
摘要： This document discusses, among other things, a multi-address Inter-Integrated Circuit (I2C) selection circuit configured to receive a number (N) of identification (ID) signals from a corresponding number (N) of ID pins of a slave I2C device and at least one of a data signal from a serial data line (SDA) of an I2C bus or a clock signal from a serial clock line (SCL) of the I2C bus, and to determine one of 4 to the power of N (4N) selectable I2C addresses using the number (N) of ID signals and at least one of the data signal or the clock signal. In an example, the multi-address I2C selection circuit can determine 4 selectable I2C addresses using a single ID signal from a single ID pin of the slave I2C device.
摘要翻译：本文件尤其讨论了多地址集成电路（I2C）选择电路，其被配置为从从属I2C设备的相应数目（N）个ID引脚接收数个（N）个标识（ID）信号以及来自I2C总线的串行数据线（SDA）的数据信号中的至少一个或来自I2C总线的串行时钟线（SCL）的时钟信号中的至少一个，并且确定N（4N）的功率中的一个）可选择的I2C地址，使用ID信号的数量（N）和数据信号或时钟信号中的至少一个。在一个例子中，多地址I2C选择电路可以使用来自从器件的单个ID引脚的单个ID信号来确定4个可选择的I2C地址。

10. 发明授权

US08335879B2 Node differentiation in multi-node electronic systems 有权
标题翻译：多节点电子系统中的节点差异化
公开(公告)号：US08335879B2
公开(公告)日：2012-12-18
申请号：US12770132
申请日：2010-04-29
申请人： Larry E Wilson , Hank Dao , Vi T Lu , Adnan T Gunduz , John D Nguyen
发明人： Larry E Wilson , Hank Dao , Vi T Lu , Adnan T Gunduz , John D Nguyen
IPC分类号： G06F13/00 , G06F3/00 , H05K7/10
CPC分类号： H05K7/1498 , G06F13/409 , G06F2213/0052
摘要： A technique for differentiating nodes in a multi-node electronic system includes establishing an intended configuration for the system, the configuration including a number of nodes to be installed and a specification of intended node locations. A node ID for each of multiple nodes to be installed in the system is established, and the multiple nodes are installed. Using the node ID established for each of the multiple nodes, a determination is made whether the multiple nodes as installed comply with the intended configuration.
摘要翻译：用于区分多节点电子系统中的节点的技术包括建立系统的预期配置，该配置包括要安装的多个节点以及预期节点位置的规范。建立系统中要安装的多个节点的节点ID，并安装多个节点。使用为每个多个节点建立的节点ID，确定安装的多个节点是否符合预期配置。

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