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1. 发明授权

US09898036B2 Apparatus and method for automatically aligning data signals and strobe signals on a source synchronous bus 有权
公开(公告)号：US09898036B2
公开(公告)日：2018-02-20
申请号：US15389538
申请日：2016-12-23
申请人： VIA TECHNOLOGIES, INC.
发明人： Vanessa Canac , James R. Lundberg
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： G06F13/4243 , G06F1/12 , G06F13/4217 , G11C7/1072 , G11C8/18
摘要： An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

2. 发明申请

US20170322587A1 METHOD FOR SCHEDULING AN AUDIO TREATMENT OF A MOTOR VEHICLE, AND ASSOCIATED OPERATING SYSTEM 审中-公开
公开(公告)号：US20170322587A1
公开(公告)日：2017-11-09
申请号：US15535035
申请日：2015-12-11
申请人： ARKAMYS
发明人： YVAN BOURMEYSTER
IPC分类号： G06F1/12 , G06F13/42 , G06F3/16
CPC分类号： G06F1/12 , G06F3/165 , G06F9/4881 , G06F13/4217
摘要： A scheduling method for an audio treatment of a motor vehicle includes elementary functions having inputs and outputs and a sampling frequency generated by a master clock. Inputs and outputs have a frame rate and a sampling frequency generated by the master clock. The elementary functions, the master clocks of which are synchronous, are grouped into synchronicity domains. A maximum treatment time is calculated which corresponds to the time necessary both to treat all the input and output frames by the elementary functions given that the inputs and outputs are produced sequentially, and also to return the elementary functions to their initial states. A scheduling of the elementary functions of each synchronicity domain is determined as a function of the maximum treatment time.

3. 发明授权

US09632964B2 Communications control system with a serial communications interface and a parallel communications interface 有权
公开(公告)号：US09632964B2
公开(公告)日：2017-04-25
申请号：US15289613
申请日：2016-10-10
申请人： Bedrock Automation Platforms Inc.
发明人： James G. Calvin , Albert Rooyakkers , Pirooz Parvarandeh
IPC分类号： G06F11/22 , G06F11/26 , G06F13/40 , G06F13/42 , G06F1/26 , G06F17/18
CPC分类号： G06F13/4282 , G06F1/26 , G06F3/002 , G06F13/00 , G06F13/14 , G06F13/4022 , G06F13/4208 , G06F13/4217 , G06F13/4221 , G06F2213/0004 , G06F2213/0022
摘要： A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

4. 发明申请

US20170103035A1 APPARATUS AND METHOD FOR LOCALLY OPTIMIZING SOURCE SYNCHRONOUS DATA STROBES 有权
公开(公告)号：US20170103035A1
公开(公告)日：2017-04-13
申请号：US15389528
申请日：2016-12-23
申请人： VIA TECHNOLOGIES, INC.
发明人： VANESSA CANAC , JAMES R. LUNDBERG
IPC分类号： G06F13/42 , G11C8/18 , G11C7/10 , G06F1/12
CPC分类号： G06F13/4243 , G06F1/12 , G06F13/4217 , G11C7/1072 , G11C8/18
摘要： An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal when an update signal is asserted, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.

5. 发明申请

US20170102733A1 APPARATUS AND METHOD FOR AUTOMATICALLY ALIGNING DATA SIGNALS AND STROBE SIGNALS ON A SOURCE SYNCRHONOUS BUS 有权
公开(公告)号：US20170102733A1
公开(公告)日：2017-04-13
申请号：US15389538
申请日：2016-12-23
申请人： VIA TECHNOLOGIES, INC.
发明人： VANESSA CANAC , JAMES R. LUNDBERG
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： G06F13/4243 , G06F1/12 , G06F13/4217 , G11C7/1072 , G11C8/18
摘要： An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

6. 发明申请

US20160239459A1 Efficient Calibration of a Low Power Parallel Data Communications Channel 有权
标题翻译：低功率并行数据通信通道的高效校准
公开(公告)号：US20160239459A1
公开(公告)日：2016-08-18
申请号：US15138210
申请日：2016-04-25
申请人： International Business Machines Corporation
发明人： Timothy O. Dickson , Daniel M. Dreps , Frank D. Ferraiolo , Douglas J. Joseph
IPC分类号： G06F15/173 , G06F15/80 , G06F13/16 , G06F11/30 , G06F13/24 , G06F13/42
CPC分类号： G06F15/17318 , G06F9/00 , G06F11/3058 , G06F13/00 , G06F13/1673 , G06F13/24 , G06F13/4217 , G06F13/4282 , G06F15/803 , G06F19/00 , H04B1/38 , H04L12/56 , Y02D10/14 , Y02D10/151
摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
摘要翻译：可校准通信链路包括多条平行线。由自动机制确定的动态变量和/或可中断间隔进行校准。校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据可能的最小的设备功能中断，如低活动水平所示。此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。

7. 发明授权

US09405720B2 Managing wait states for memory access 有权
标题翻译：管理内存访问的等待状态
公开(公告)号：US09405720B2
公开(公告)日：2016-08-02
申请号：US13941671
申请日：2013-07-15
申请人： Atmel Corporation
发明人： Frode Milch Pedersen , Sebastien Jouin , Ian Fullerton
IPC分类号： G06F13/42 , G06F13/16
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0679 , G06F13/1689 , G06F13/4217 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.
摘要翻译：从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。接收总线系统时钟信号。评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。产生基于调整后的等待状态触发的总线系统数据就绪信号。当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

8. 发明申请

US20160162434A1 DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL 有权
标题翻译：具有可编程终止级别的动态总线反相
公开(公告)号：US20160162434A1
公开(公告)日：2016-06-09
申请号：US14565176
申请日：2014-12-09
申请人： Christopher P. Mozak , James A. McCall , Bryan K. Casper
发明人： Christopher P. Mozak , James A. McCall , Bryan K. Casper
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
摘要： Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
摘要翻译：动态总线反演（DBI）可编程级别为1和0的比例。发送装置识别要发送的信号（“非反相信号”）的非反相版本中的1和0的数量和/或比率，以及信号的反转版本中的数字和/或比例的1和0“ 反转信号“）。发送装置可以计算反相信号中的非反相信号中的1和0的差是否相同，或者反转信号中的1和0的差是否将计算的平均比值提升到更靠近目标比的1。发送装置发送实现的信号，使所计算的平均比率更接近目标比率。

9. 发明授权

US09060407B2 Portable lighting device with reconfigurable user interface 有权
标题翻译：便携式照明设备，具有可重新配置的用户界面
公开(公告)号：US09060407B2
公开(公告)日：2015-06-16
申请号：US12928519
申请日：2010-12-13
申请人： Stacey H. West
发明人： Stacey H. West
IPC分类号： H05B37/00 , H05B33/08 , H05B37/02
CPC分类号： G06F3/0611 , F21L4/00 , F21V23/0428 , G06F3/0655 , G06F3/0679 , G06F13/1689 , G06F13/4217 , G06F13/4243 , H05B33/0845 , H05B33/0854 , H05B37/0209 , Y02B20/40 , Y02D10/14 , Y02D10/151
摘要： A portable lighting device that provides different user interfaces that may be selected by the user. Each user interface may provide one or more operational modes, such as on mode, power save mode, strobe mode or momentary mode. After a user interface is selected, the user may select on of the operational modes. The portable lighting device may be a flashlight.
摘要翻译：提供可由用户选择的不同用户界面的便携式照明设备。每个用户界面可以提供一种或多种操作模式，诸如在模式，省电模式，选通模式或瞬时模式。在选择用户界面之后，用户可以选择操作模式。便携式照明装置可以是手电筒。

10. 发明申请

US20150019790A1 COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE 审中-公开
标题翻译：具有串行通信接口和并行通信接口的通信控制系统
公开(公告)号：US20150019790A1
公开(公告)日：2015-01-15
申请号：US14502006
申请日：2014-09-30
申请人： Bedrock Automation Platforms Inc.
发明人： James G. Calvin , Albert Rooyakkers , Pirooz Parvarandeh
IPC分类号： G06F13/40 , G06F1/26
CPC分类号： G06F13/4282 , G06F1/26 , G06F3/002 , G06F13/00 , G06F13/14 , G06F13/4022 , G06F13/4208 , G06F13/4217 , G06F13/4221 , G06F2213/0004 , G06F2213/0022
摘要： A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
摘要翻译：公开了一种通信控制系统，其包括用于将多个输入/输出模块与控制模块耦合的串行通信接口和并行通信接口。串行通信接口被配置为并行地将多个输入/输出模块连接到控制模块以在多个输入/输出模块和控制模块之间传送信息，并且并行通信接口被配置为分开地连接多个输入/输出模块到控制模块以在多个输入/输出模块和控制模块之间传送信息，并在多个输入/输出模块中的各个输入/输出模块之间传送信息。串行通信接口可以包括多点总线，并且并行通信接口可以包括交叉开关。

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