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1. 发明申请

US20190121754A1 DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTAIN PROGRAMMABLE TARGET RATIO OF ONES AND ZEROS IN SIGNAL LINES 审中-公开
公开(公告)号：US20190121754A1
公开(公告)日：2019-04-25
申请号：US16028137
申请日：2018-07-05
申请人： Intel Corporation
发明人： Christopher P. MOZAK , James A. McCALL , Bryan K. CASPER
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
摘要： Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

2. 发明申请

US20160013958A1 DATA LINK POWER REDUCTION TECHNIQUE USING BIPOLAR PULSE AMPLITUDE MODULATION 有权
标题翻译：数据链路功率降低技术使用双极脉冲放大调制
公开(公告)号：US20160013958A1
公开(公告)日：2016-01-14
申请号：US14328556
申请日：2014-07-10
申请人： QUALCOMM Incorporated
发明人： Lalan Jee Mishra , Timothy Mowry Hollis
IPC分类号： H04L25/49 , H04L25/06 , H04L27/06
CPC分类号： H04L25/4927 , H04L25/0292 , H04L25/0298 , H04L25/06 , H04L25/4915 , H04L25/4917 , H04L27/06
摘要： High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.
摘要翻译：处理器和片外DRAM之间的高速数据链路利用脉冲幅度调制（PAM）信号来提高SoC中给定带宽和资源预算的数据速率。然而，处理器和DRAM之间的传输线接口中使用的终端电阻在PAM信令期间消耗大量的功率。通过在接地端子和终端电阻之间增加一个偏压源，终端电阻器用作确定信号电平的基准的“底电压”可能会提高。提高地板电压会降低终端电阻两端的电压，从而降低功耗。偏置源被调整到PAM信号的最大幅度的各种增量。 PAM信令的最大幅度的一半的地电压在接收机中产生最小功耗。另外，数据反转预编码可以与底层电压调整相连接，以进一步最大化接口的功率节省。

3. 发明申请

US20150349921A1 ENHANCED SIGNAL INTEGRITY AND COMMUNICATION UTILIZING OPTIMIZED CODE TABLE SIGNALING 有权
标题翻译：使用优化代码表信号的增强信号完整性和通信
公开(公告)号：US20150349921A1
公开(公告)日：2015-12-03
申请号：US14705626
申请日：2015-05-06
申请人： OptCTS, Inc.
发明人： Bruce Conway
IPC分类号： H04L1/00
CPC分类号： H03M7/3082 , H03M7/42 , H03M7/6052 , H03M13/00 , H03M13/11 , H03M13/25 , H03M13/251 , H03M13/353 , H03M13/611 , H04L1/0009 , H04L1/0041 , H04L1/0042 , H04L1/0043 , H04L1/006 , H04L1/0061 , H04L1/0075 , H04L9/00 , H04L25/4915 , H04L27/3416
摘要： In various embodiments, a computer-implemented method for optimized data transfer utilizing optimized code table signaling is disclosed. In one embodiment, a computer-implemented method comprises receiving, by a processor, a digital bit stream and transforming, by the processor, the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof. The computer-implemented method further comprises providing, by the processor, the encoded digital bit stream to a transmission system for transmission and establishing, by the processor, signal integrity by utilizing pre-coordinated, pre-distributed information to limit the transmission to an intended sender-receiver pair. The intended sender-receiver pair comprises the pre-coordinated, pre-distributed information.
摘要翻译：在各种实施例中，公开了一种利用优化代码表信令优化数据传输的计算机实现的方法。在一个实施例中，计算机实现的方法包括由处理器接收数字比特流，并且由处理器将数字比特流转换成编码的数字比特流。编码数字比特流包括网关信道，复合信道或数据信道中的至少一个及其任何组合。计算机实现的方法还包括由处理器将经编码的数字比特流提供给传输系统，以便由处理器通过利用预先协调的预分布式信息来将信号传输限制到预期的传输和建立信号完整性发送方 - 接收方对。预期的发送者 - 接收者对包括预协调的预分布信息。

4. 发明授权

US09172567B2 Methods and apparatus to reduce signaling power 有权
标题翻译：减少信号功率的方法和装置
公开(公告)号：US09172567B2
公开(公告)日：2015-10-27
申请号：US14089683
申请日：2013-11-25
申请人： QUALCOMM Incorporated
发明人： Timothy Mowry Hollis
IPC分类号： H04L25/49 , G06F13/38 , H03M5/02
CPC分类号： H04L25/4917 , G06F13/38 , H03M5/02 , H04L25/4915
摘要： System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.
摘要翻译：描述了减少由多级编码通信链路消耗的功率的系统，方法和装置。在一个示例中，4级脉冲幅度调制编码传输的不同逻辑状态消耗比其他逻辑状态更大的功率。多比特数据符号中的第一逻辑状态中的主比特的分数可以确定在传输之前主比特是否被反转。在多位数据符号中的第一逻辑状态中的副位的分数可以确定辅助位在传输之前是否被反转。主位可以被交换，次级位比第一逻辑状态中的主位更多次次位处于第一逻辑状态。

5. 发明授权

US09031156B2 Enhanced signal integrity and communication utilizing optimized code table signaling 有权
标题翻译：增强的信号完整性和利用优化代码表信令的通信
公开(公告)号：US09031156B2
公开(公告)日：2015-05-12
申请号：US14099180
申请日：2013-12-06
申请人： OptCTS, Inc.
发明人： Bruce Conway
IPC分类号： H04L27/00 , H04L1/00 , H04L25/49
CPC分类号： H03M7/3082 , H03M7/42 , H03M7/6052 , H03M13/00 , H03M13/11 , H03M13/25 , H03M13/251 , H03M13/353 , H03M13/611 , H04L1/0009 , H04L1/0041 , H04L1/0042 , H04L1/0043 , H04L1/006 , H04L1/0061 , H04L1/0075 , H04L9/00 , H04L25/4915 , H04L27/3416
摘要： In various embodiments, a computer-implemented method for optimized data transfer utilizing optimized code table signaling is disclosed. In one embodiment, a computer-implemented method comprises receiving, by a processor, a digital bit stream and transforming, by the processor, the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof. The computer-implemented method further comprises providing, by the processor, the encoded digital bit stream to a transmission system for transmission and establishing, by the processor, signal integrity by utilizing pre-coordinated, pre-distributed information to limit the transmission to an intended sender-receiver pair. The intended sender-receiver pair comprises the pre-coordinated, pre-distributed information.
摘要翻译：在各种实施例中，公开了一种利用优化代码表信令优化数据传输的计算机实现的方法。在一个实施例中，计算机实现的方法包括由处理器接收数字比特流，并且由处理器将数字比特流转换成编码的数字比特流。编码数字比特流包括网关信道，复合信道或数据信道中的至少一个及其任何组合。计算机实现的方法还包括由处理器将经编码的数字比特流提供给传输系统，以便由处理器通过利用预先协调的预分布式信息来将信号的传输限制到预期的传输和建立信号完整性发送方 - 接收方对。预期的发送者 - 接收者对包括预协调的预分布信息。

6. 发明授权

US08581755B2 Multiple word data bus inversion 有权
标题翻译：多字数据总线反转
公开(公告)号：US08581755B2
公开(公告)日：2013-11-12
申请号：US13502474
申请日：2010-10-08
申请人： Aliazam Abbasfar , John Wilson
发明人： Aliazam Abbasfar , John Wilson
IPC分类号： H03M5/00
CPC分类号： H04L25/4915 , G06F13/4072 , G06F13/4204 , G11C7/1006 , H04L25/0272
摘要： A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.
摘要翻译：用于将数据从一个电路传输到另一电路的数据编码方案考虑组合的多个字的汉明权重来确定是否反转要发送的单个字。多字数据编码方案基于组合的多个字中的总HW执行数据反转来执行DBI编码。基于每个单词的个体汉明重量的总和，决定反转或不反转每个多个单词。这种编码的优点在于，当编码数据具有通过宽并行总线从一个电路发送到另一个电路的大量字时，SSO噪声显着降低。

7. 发明授权

US08514895B2 Bit-stuffing method for crosstalk avoidance in high-speed buses 有权
标题翻译：高速总线串扰避免的位填充方法
公开(公告)号：US08514895B2
公开(公告)日：2013-08-20
申请号：US12853444
申请日：2010-08-10
申请人： Cheng-Shang Chang , Jay Cheng , Tien-Ke Huang , Xuan-Chao Huang , Duan-Shin Lee , Chao-Yi Chen
发明人： Cheng-Shang Chang , Jay Cheng , Tien-Ke Huang , Xuan-Chao Huang , Duan-Shin Lee , Chao-Yi Chen
IPC分类号： H04J3/07
CPC分类号： H04L25/4915 , H04L25/0272 , H04L25/03343 , H04L25/085 , H04L2025/03426
摘要： This invention discloses a bit-stuffing method for crosstalk avoidance in high-speed buses, which comprises the steps of inputting a plurality of data bit streams in parallel to a data input buffer; the data input buffer sequentially inputting data bits of the data bit streams to a bit-switching unit, and the bit-switching unit switching the data bits to generate bit-switched data; parallelly inputting the bit-switched data to a bit-stuffing encoding unit; the bit-stuffing encoding unit performing bit-stuffing encoding on the bit-switched data to generate encoded data bits and inputting the encoded data bits to an encoded data buffer; and the encoded data buffer outputting the encoded data to a high-speed bus. The encoded data bits passed through the high-speed bus are decoded using a bit-removing method to recover the data bit streams.
摘要翻译：本发明公开了一种用于高速总线中的串扰避免的位填充方法，包括以下步骤：将多个数据比特流并行地输入到数据输入缓冲器; 数据输入缓冲器顺序地将数据位流的数据位输入到位切换单元，并且位切换单元切换数据位以产生位切换数据; 将比特交换数据并行输入到填充编码单元; 所述比特填充编码单元对所述比特交换数据执行比特填充编码，以生成编码数据比特，并将编码数据比特输入到编码数据缓冲器; 并且编码数据缓冲器将编码数据输出到高速总线。通过高速总线传送的编码数据位使用位去除方法进行解码，以恢复数据位流。

8. 发明授权

US08498344B2 Frequency responsive bus coding 有权
标题翻译：频率响应总线编码
公开(公告)号：US08498344B2
公开(公告)日：2013-07-30
申请号：US12999495
申请日：2009-06-18
申请人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
发明人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.
摘要翻译：数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

9. 发明授权

US08320444B2 Transmission apparatus and method, reception apparatus and method, and program 失效
标题翻译：发送装置及方法，接收装置和方法以及程序
公开(公告)号：US08320444B2
公开(公告)日：2012-11-27
申请号：US12433241
申请日：2009-04-30
申请人： Takashi Nakanishi , Masato Kikuchi , Shunsuke Mochizuki , Masahiro Yoshioka , Ryosuke Araki , Masaki Handa , Hiroshi Ichiki , Tetsujiro Kondo
发明人： Takashi Nakanishi , Masato Kikuchi , Shunsuke Mochizuki , Masahiro Yoshioka , Ryosuke Araki , Masaki Handa , Hiroshi Ichiki , Tetsujiro Kondo
IPC分类号： H03K7/04
CPC分类号： H04L25/0224 , H04L25/0244 , H04L25/4915
摘要： A transmission apparatus includes a modulating section configured to modulate a baseband signal by using a carrier wave; a determining section configured to determine a pattern of the carrier wave, in accordance with a characteristic of a transmission channel on which a waveform represented by a signal value of a specific symbol is stationarily distorted according to a value of a symbol transmitted before or after the specific symbol; and a transmitting section configured to transmit a modulation signal through the transmission channel, the modulation signal being obtained by modulation using the determined carrier-wave pattern.
摘要翻译：发送装置包括：调制部，被配置为通过使用载波来调制基带信号; 确定部分，被配置为根据传输信道的特性确定载波的模式，在该传输信道上，由特定符号的信号值表示的波形根据在特定符号的信号值之前或之后发送的符号的值而被静态失真具体符号以及发送部，被配置为通过所述传输信道发送调制信号，所述调制信号通过使用所确定的载波模式进行调制获得。

10. 发明申请

US20120117447A1 Data transmission 有权
标题翻译：数据传输
公开(公告)号：US20120117447A1
公开(公告)日：2012-05-10
申请号：US13317782
申请日：2011-10-28
申请人： Tsugio Takahashi
发明人： Tsugio Takahashi
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L25/4915 , H03M13/05 , H04L1/0045 , H04L1/0057
摘要： If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.
摘要翻译：如果64位宽度数据同时变化的位数超过阈值，则以每个位的极性反转的方式输出数据。否则，输出数据。对输出的数据和反转指示信号给出7位宽度的纠错码，该指示信号指示改变的位的数目是否已超过阈值。使用发送的纠错码对数据和反转指令信号执行错误代码校正。如果已经执行了错误代码校正的反转指令信号指示改变的位的数量已经超过阈值，则输出已执行错误代码校正的数据，每个位的极性反转。否则，输出执行了错误代码校正的数据。

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