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1. 发明授权

US12032511B2 Synchronization in multi-chip systems 有权
公开(公告)号：US12032511B2
公开(公告)日：2024-07-09
申请号：US17844888
申请日：2022-06-21
申请人： Google LLC
发明人： Michial Allen Gunter , Denis Baylor , Clifford Biffle , Charles Ross
IPC分类号： G06F15/173 , G06F15/17 , G06N3/063 , H04L12/44 , H04L43/0864
CPC分类号： G06F15/17312 , G06F15/17 , G06F15/17337 , H04L12/44 , G06N3/063 , H04L43/0864
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

2. 发明公开

US20240160476A1 RESPONDING TO APPLICATION DEMAND IN A SYSTEM THAT USES PROGRAMMABLE LOGIC COMPONENTS 审中-公开
公开(公告)号：US20240160476A1
公开(公告)日：2024-05-16
申请号：US18423184
申请日：2024-01-25
申请人： ThroughPuter, Inc.
发明人： Mark Henrik Sandstrom
IPC分类号： G06F9/50 , G06F9/46 , G06F9/48 , G06F9/54 , G06F15/173 , H04L49/15
CPC分类号： G06F9/5011 , G06F9/46 , G06F9/4881 , G06F9/5016 , G06F9/5027 , G06F9/5038 , G06F9/505 , G06F9/54 , G06F9/544 , G06F9/546 , G06F15/17337 , H04L49/15
摘要： Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

3. 发明授权

US11960436B2 Multi-processor synchronization 有权
公开(公告)号：US11960436B2
公开(公告)日：2024-04-16
申请号：US17732766
申请日：2022-04-29
申请人： Microsoft Technology Licensing, LLC
发明人： Nadav Shlomo Ben-Amram , Netanel Hadad , Liran Biber
IPC分类号： G06F9/02 , G06F15/173
CPC分类号： G06F15/17325 , G06F15/17337
摘要： A method of synchronizing system state data is provided. The method includes executing a first processor based on initial state data during an update cycle, wherein the initial state data represents a state of the system prior to initiation of the update cycle, detecting changes in state of the system by the first processor using sensors, the changes in state being added to a record of modified state data until a predefined progress position within the update cycle, designating the modified state data as next state data, based on reaching the predefined progress position within the update cycle, and transitioning from execution of the first processor based on the initial state data to execution of the first processor based on the next state data, based on completion of the update cycle.

4. 发明申请

US20180300178A1 Application Load Adaptive Multi-stage Parallel Data Processing Architecture 审中-公开
公开(公告)号：US20180300178A1
公开(公告)日：2018-10-18
申请号：US16014674
申请日：2018-06-21
申请人： Mark Henrik Sandstrom
发明人： Mark Henrik Sandstrom
IPC分类号： G06F9/50 , G06F9/54 , G06F9/48
CPC分类号： G06F9/5011 , G06F9/46 , G06F9/4881 , G06F9/5016 , G06F9/5027 , G06F9/5038 , G06F9/505 , G06F9/54 , G06F9/544 , G06F9/546 , G06F15/17337 , H04L49/15
摘要： Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

5. 发明授权

US10002096B1 Flow control in a parallel processing environment 有权
公开(公告)号：US10002096B1
公开(公告)日：2018-06-19
申请号：US15143754
申请日：2016-05-02
申请人： Mellanox Technologies Ltd.
发明人： David M. Wentzlaff
IPC分类号： G06F13/40 , G06F13/42 , G06F13/16
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0656 , G06F3/0673 , G06F13/1673 , G06F13/4291 , G06F15/17337 , G06F15/17343 , Y02D10/14 , Y02D10/151
摘要： The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.

6. 发明申请

US20170337156A1 COMPUTING MACHINE ARCHITECTURE FOR MATRIX AND ARRAY PROCESSING 审中-公开
公开(公告)号：US20170337156A1
公开(公告)日：2017-11-23
申请号：US15488494
申请日：2017-04-16
申请人： SITARAM YADAVALLI
发明人： SITARAM YADAVALLI
IPC分类号： G06F15/80 , H04L12/933 , G06F15/173 , G06F9/52
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30149 , G06F9/30167 , G06F9/30185 , G06F9/345 , G06F9/52 , G06F15/17325 , G06F15/17337 , G06F15/8023 , H04L49/101 , H04L49/15
摘要： This invention discloses a novel paradigm, method and apparatus for Matrix Computing which include a novel machine architecture with an embedded storage space for holding matrices and arrays for computing which can be accessed by its columns or by its rows or both concurrently. A large capacity multi length instruction set with instructions and methods to load, store and compute with these matrices and arrays are also disclosed; a method and apparatus to secure, share, lock and unlock this embedded space for matrices under the control of an Operating System or a Virtual Machine Monitor by a plurality of threads and processes are also disclosed. A novel method and apparatus to handle immediate operands used by Immediate Instructions are also disclosed. The structure of the instructions with some key fields and a method for determining instruction length easily are also disclosed.

7. 发明授权

US09690647B2 Information processing apparatus and method of diagnosis 有权
公开(公告)号：US09690647B2
公开(公告)日：2017-06-27
申请号：US14926407
申请日：2015-10-29
申请人： FUJITSU LIMITED
发明人： Yasuhiko Uchida
IPC分类号： G06F11/00 , G06F11/07 , G06F13/00 , G06F15/00 , G06F11/22
CPC分类号： G06F11/079 , G06F11/0724 , G06F11/0745 , G06F11/22 , G06F11/221 , G06F11/2284 , G06F13/00 , G06F15/00 , G06F15/17337
摘要： A building block includes an XSCF that controls the building block and an XBU that performs communication with another building block. The XSCF includes a hardware controller that instructs crossbar diagnosis to the XBU. The XBU includes a port information storage unit that stores therein diagnosis information related to the crossbar diagnosis and a test module that performs the crossbar diagnosis on the basis of the diagnosis information stored in the port information storage unit.

8. 发明申请

US20160328357A1 COMPUTER SUBSYSTEM AND COMPUTER SYSTEM WITH COMPOSITE NODES IN AN INTERCONNECTION STRUCTURE 审中-公开
标题翻译：计算机子系统与计算机系统与互连结构中的复合节点
公开(公告)号：US20160328357A1
公开(公告)日：2016-11-10
申请号：US15150419
申请日：2016-05-09
申请人： HUAWEI TECHNOLOGIES CO.,LTD.
发明人： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
IPC分类号： G06F15/80 , G06F13/42
CPC分类号： G06F15/80 , G06F13/4221 , G06F15/167 , G06F15/17337
摘要： The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
摘要翻译：本发明提供一种计算机子系统和计算机系统。计算机子系统包括L个复合节点，每个复合节点包括M个基本节点，每个基本节点包括N个中央处理单元（CPU）和一个节点控制器。每个基本节点中的任何两个CPU都是互连的。每个基本节点中的每个CPU都连接到基本节点中的节点控制器。每个基本节点中的节点控制器具有路由功能。 M个基本节点中的任何两个节点控制器互连。通过节点控制器之间的连接形成的L个复合节点之间的连接使得任何两个节点控制器之间的通信不超过三跳。根据本发明的实施例的计算机子系统和计算机系统可以减少互连芯片的种类和数量，并且简化系统的互连结构，从而提高系统的可靠性。

9. 发明申请

US20160259756A1 CIRCUITS AND METHODS FOR INTER-PROCESSOR COMMUNICATION 审中-公开
标题翻译：用于处理器间通信的电路和方法
公开(公告)号：US20160259756A1
公开(公告)日：2016-09-08
申请号：US14638692
申请日：2015-03-04
申请人： XILINX, INC.
发明人： Sagheer Ahmad , Soren Brinkmann
IPC分类号： G06F15/167 , G06F13/16 , G06F13/42 , G06F12/14 , G06F13/24
CPC分类号： G06F15/167 , G06F12/1425 , G06F13/1673 , G06F13/24 , G06F13/4221 , G06F15/17 , G06F15/17337 , G06F2212/1052 , Y02D10/14 , Y02D10/151
摘要： Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.
摘要翻译：各种示例性实现涉及用于在不同处理器电路之间进行通信的电路和方法。根据示例实现，电路装置包括多个处理器电路和处理器间通信电路。处理器间通信电路被配置为为每对处理器电路提供一对处理器电路之间的相应通信信道。处理器间通信电路包括多个缓冲器，包括用于每个通信信道的相应的第一缓冲器和相应的第二缓冲器。包括在处理器间通信电路中的访问控制电路被配置为限制对第一处理器电路的相应的第一缓冲区的写入访问，并限制对第二处理器电路的各个第二缓冲区的写入访问。

10. 发明授权

US09436639B1 Full bandwidth packet handling with server systems including offload processors 有权
标题翻译：带有服务器系统的全带宽数据包处理，包括卸载处理器
公开(公告)号：US09436639B1
公开(公告)日：2016-09-06
申请号：US13931907
申请日：2013-06-29
申请人： Xockets, Inc.
发明人： Parin Bhadrik Dalal , Stephen Paul Belair
IPC分类号： G06F13/00 , G06F13/40 , G06F13/16 , G06F15/16 , H04L29/08
CPC分类号： G06F13/1652 , G06F9/3877 , G06F9/461 , G06F9/4843 , G06F12/0815 , G06F12/0875 , G06F13/16 , G06F13/285 , G06F13/362 , G06F13/4022 , G06F13/4068 , G06F15/161 , G06F15/17337 , H04L29/08135 , H04L29/08549 , H04L47/193 , H04L47/2441 , H04L47/56 , H04L47/624 , H04L47/6295 , H04L49/40 , H04L49/90 , H04L61/103 , H04L61/2592 , H04L61/6086 , Y02D10/14 , Y02D10/151
摘要： A distributed system server system for a packet processing without top of rack (TOR) units is disclosed. The system can include a plurality of servers, each having at least one host processor, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module is connected directly to a second offload processor module through respective IO ports, the first and second offload processors configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without TOR units for an inter-server connection.
摘要翻译：公开了一种用于无顶架（TOR）单元的分组处理的分布式系统服务器系统。该系统可以包括多个服务器，每个服务器具有至少一个主机处理器和多个卸载处理器模块，每个卸载处理器模块具有输入 - 输出（IO）端口和多个卸载处理器，其中第一卸载处理器模块是第一和第二卸载处理器被配置为在至少第一卸载处理器模块和第二卸载处理器模块之间提供双向网络分组流，以及至少一个主机处理器，其不具有用于服务器间的TOR单元连接。

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