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1. 发明授权

US12034373B2 Electronic devices and methods of controlling power in electronic devices 有权
公开(公告)号：US12034373B2
公开(公告)日：2024-07-09
申请号：US17575249
申请日：2022-01-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sangwook Park , Joonseok Park , Jongjin Lee , Horang Jang
IPC分类号： H02M3/158 , G06F13/42 , H02M3/157
CPC分类号： H02M3/1584 , G06F13/4282 , H02M3/157 , G06F2213/0016 , G06F2213/0038
摘要： An electronic device includes a system on chip (SoC) and a power management integrated circuit (PMIC). The SoC includes a plurality of power domains and a dynamic voltage and frequency scaling (DVFS) controller which performs DVFS on the power domains The PMIC includes direct current (DC)-DC converters and a control logic which controls the plurality of DC-DC converters, and each of the DC-DC converters provides a corresponding output voltage to a respective one of the power domains. The control logic designates a target DC-DC converter which provides a target output voltage having a target level as a global DC-DC converter and provides the target output voltage to a power domain corresponding the global DC-DC converter and to at least one first power domain consuming the target output voltage, from among the plurality of power domains, by sharing the target output voltage provided by the global DC-DC converter.

2. 发明授权

US12013798B2 Method of data synchronization and redundant server system 有权
公开(公告)号：US12013798B2
公开(公告)日：2024-06-18
申请号：US18052559
申请日：2022-11-03
申请人： Mitac Computing Technology Corporation
发明人： Chin-Hung Tan , Heng-Chia Hsu , Chien-Chung Wang , Yu-Shu Yeh , Chen-Yin Lin
IPC分类号： G06F9/445 , G06F13/16
CPC分类号： G06F13/1668 , G06F9/44505 , G06F2213/0016
摘要： A method of data synchronization is to be implemented by a redundant server system including an active input/output module (IOM) and a passive IOM. The method includes: allocating a primary transfer buffer in the active IOM; allocating a secondary transfer buffer in the passive IOM; collecting pieces of secondary dedicated-sensor data, and storing the pieces of secondary dedicated-sensor data in the primary transfer buffer at once; collecting pieces of primary dedicated-sensor data; after the pieces of primary dedicated-sensor data have been collected, updating the primary state data based on the pieces of primary dedicated-sensor data thus collected and the pieces of secondary dedicated-sensor data stored in the primary transfer buffer at once, and storing the primary state data thus updated in the secondary transfer buffer; and updating the secondary state data based on the primary state data that have been updated and that are stored in the secondary transfer buffer.

3. 发明授权

US12007930B2 Low voltage drive circuit with drive sense and methods for use therewith 有权
公开(公告)号：US12007930B2
公开(公告)日：2024-06-11
申请号：US18319283
申请日：2023-05-17
申请人： SigmaSense, LLC.
发明人： Richard Stuart Seger, Jr. , Daniel Keith Van Ostrand , Gerald Dale Morrison , Timothy W. Markison
IPC分类号： G06F13/40 , H04L7/04 , H04L12/40 , H03F3/45 , H04L25/02
CPC分类号： G06F13/4072 , H04L7/04 , H04L12/40045 , G06F2213/0016 , H03F3/45 , H04L25/0282
摘要： A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

4. 发明公开

US20240143443A1 METHOD AND APPARATUS FOR REPAIRING HANGING IN COMMUNICATION BUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM 审中-公开
公开(公告)号：US20240143443A1
公开(公告)日：2024-05-02
申请号：US18281290
申请日：2022-05-26
申请人： INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
发明人： Weibin KONG , Kaixin SONG , Changshun WU
IPC分类号： G06F11/14 , G06F13/42
CPC分类号： G06F11/141 , G06F13/4291 , G06F2213/0016
摘要： The present disclosure discloses a method for repairing hanging-up of a communication bus, an apparatus, an electronic device and a storage medium. The method includes: detecting a communication situation between the central processing unit and a baseband processing unit; when the communication situation is used to indicate a communication fault between the central processing unit and the baseband processing unit, determining a target hanging-up event generated by the communication bus deployed between the central processing unit and the baseband processing unit; obtaining a target repairing operation corresponding to the target hanging-up event; and according to the target repairing operation, repairing the communication bus.

5. 发明授权

US11928066B2 I2C bridge device 有权
公开(公告)号：US11928066B2
公开(公告)日：2024-03-12
申请号：US16470264
申请日：2017-12-15
申请人： Iristick NV
发明人： Jasper Van Bourgognie , Vianney Le Clément de Saint-Marcq , Riemer Grootjans , Peter Verstraeten
IPC分类号： G06F13/40 , G06F13/42 , H04L5/14
CPC分类号： G06F13/4045 , G06F13/4031 , G06F13/4291 , H04L5/14 , G06F2213/0016
摘要： The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged for translating an I2C event to a message and for forwarding said message to the module at the other side of the bridge device via said internal bridge interfaces, said module at the other side being arranged for further transmitting said message as an I2C event towards the I2C bus at the other side of the bridge device, and whereby said parent module and said child module are further each arranged for holding the communication towards the respective I2C bus by stretching a clock line on their respective I2C bus until a message, based on an event occurring on the I2C bus at the other side of the bridge device and instructing continuation of the communication, is received via said internal bridge interfaces from the module at the other side of the bridge device.

6. 发明授权

US11924579B1 FPD-link IV video generator system 有权
公开(公告)号：US11924579B1
公开(公告)日：2024-03-05
申请号：US18372839
申请日：2023-09-26
申请人： N.S. International, Ltd.
发明人： Karthikeyan Palanisamy , Kumaresan Thiyagarajan , Rajvel Murugesan , Rajadeepan Murugesan , Daniel Sanchez , Slavko Bogoevski , Syed Nabi
IPC分类号： H04N7/18 , G06F1/18 , G06F13/38 , G06F13/40 , G06F13/42 , H04N7/10 , H04N17/00
CPC分类号： H04N7/102 , G06F1/189 , G06F13/382 , G06F13/4027 , G06F13/4282 , H04N7/183 , H04N17/004 , G06F2213/0016 , G06F2213/0042
摘要： An apparatus for generating FPD-link IV signals in automobiles. The apparatus includes a USB to I2C converter allowing USB interfaced commands and Ethernet interfaced commands to configure and update a single board computer, an FPD-link IV Serializer and the single board computer that produce a video signal to FPD-link IV outputs. The single board computer stores video timing parameters (EDID) for the Device Under Test as well.

7. 发明授权

US11892871B2 Clock synchronization system and operation method thereof capable of synchronizing operation time of internal circuits 有权
公开(公告)号：US11892871B2
公开(公告)日：2024-02-06
申请号：US17684443
申请日：2022-03-02
申请人： Realtek Semiconductor Corp.
发明人： Po-Lin Wei , Ching-Lung Chen
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： G06F1/12 , G06F13/4291 , G06F2213/0016 , G06F2213/0042
摘要： A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.

8. 发明授权

US11847226B1 Baseboard Management Controller (BMC)-based security processor 有权
公开(公告)号：US11847226B1
公开(公告)日：2023-12-19
申请号：US17104910
申请日：2020-11-25
申请人： AMERICAN MEGATRENDS INTERNATIONAL, LLC
发明人： Stefano Righi , Umasankar Mondal , Sanjoy Maity
IPC分类号： G06F21/00 , G06F21/57 , G06F13/42 , G06F21/53 , G06F13/40 , G06F21/74
CPC分类号： G06F21/572 , G06F13/4063 , G06F13/4282 , G06F21/53 , G06F21/74 , G06F2213/0016 , G06F2213/0038
摘要： Technologies are described herein for providing a Baseboard Management Controller (“BMC”)-based security processor. The disclosed BMC-based security processor can provide a hardware Root of Trust (“RoT”) for a computing platform without the addition of specialized silicon to the platform and while minimizing the number of attack points. The disclosed BMC-based security processor can also provide functionality for securely filtering requests made on certain buses in a computing platform. Through implementations of the features identified briefly above, and others described herein, various technical benefits can be achieved such as, but not limited to, increased security as compared to previous computing systems that utilize a BMC to provide a hardware RoT and reduced complexity and cost as compared to previous computing systems that utilize a separate hardware device, such as a Field Programmable Gate Array (“FPGA”) or a microcontroller, to provide a hardware RoT.

9. 发明授权

US11841810B2 Communication interface buffer with hot-swap protection 有权
公开(公告)号：US11841810B2
公开(公告)日：2023-12-12
申请号：US17244370
申请日：2021-04-29
申请人： Texas Instruments Incorporated
发明人： Suvadip Banerjee , Sreeram Subramanyam Nasum , Anant Shankar Kamath
IPC分类号： G06F13/20 , G06F13/40 , H03K17/687 , G06F13/42
CPC分类号： G06F13/20 , G06F13/4086 , H03K17/6871 , G06F13/4282 , G06F2213/0016
摘要： A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

10. 发明公开

US20230385225A1 COMMUNICATION DEVICE AND COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20230385225A1
公开(公告)日：2023-11-30
申请号：US18320662
申请日：2023-05-19
申请人： Sony Semiconductor Solutions Corporation
发明人： Junya Yamada , Toshihisa Hyakudai , Satoshi Ota
IPC分类号： G06F13/42 , H04L69/22
CPC分类号： G06F13/4282 , H04L69/22 , G06F2213/0016
摘要： The memory capacity for storing address information etc. of an I2C communication instrument, as well as the number of encoders and decoders can be reduced.
A communication device to establish communication between a first I2C communication instrument and a second I2C communication instrument connected to a communication partner device, includes: an encoder that generates Header Packet Data including a target ID of the communication partner device and I2C Packet Data including a slave address and an offset address of the second I2C communication instrument; a communication unit that transmits a transmission packet including the Header Packet Data and the I2C Packet Data generated by the encoder to the communication partner device by a TDD communication scheme and receives a reception packet from the communication partner device by the TDD communication scheme; and a decoder that generates the I2C Packet Data from the reception packet.

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