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1. 发明申请

US20180217951A1 Systems, Methods, and Computer-Readable Media for Managing Instruction Fetch in Virtual Computing Environments 审中-公开
公开(公告)号：US20180217951A1
公开(公告)日：2018-08-02
申请号：US15936364
申请日：2018-03-26
申请人： SanDisk Technologies LLC
发明人： Shay Benisty , Rajesh Koul
IPC分类号： G06F13/16
CPC分类号： G06F13/1642 , G06F2213/16 , G06F2213/24
摘要： Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.

2. 发明申请

US20180217777A1 Overflow Region Memory Management 审中-公开
公开(公告)号：US20180217777A1
公开(公告)日：2018-08-02
申请号：US15473311
申请日：2017-03-29
申请人： Samsung Electronics Co., Ltd.
发明人： Dongyan Jiang , Changhui Lin , Krishna Malladi , Jongmin Gim , Hongzhong Zheng
IPC分类号： G06F3/06 , G06F12/10 , G06F13/16 , G06F13/42
CPC分类号： G06F3/0644 , G06F3/0604 , G06F3/0619 , G06F3/0641 , G06F3/0656 , G06F3/0665 , G06F3/0683 , G06F12/10 , G06F13/1673 , G06F13/4282 , G06F2212/65 , G06F2213/16
摘要： A memory module includes a host interface configured to provide an interface to a host computer; one or more memory devices; a deduplication engine configured to provide a virtual memory capacity of the memory module that is larger than a physical size of the one or more memory devices; a memory controller for controlling access to the one or more memory devices; a volatile memory comprising a hash table, an overflow memory region, and a credit unit, wherein the overflow memory region stores user data when a hash collision occurs or the hash table is full, and wherein the credit unit stores an address of an invalidated entry in the overflow memory region; and a control logic is configured to control the overflow memory region and the credit unit and generate a warning indicating a status of the overflow memory region and the credit unit.

3. 发明申请

US20180113820A1 SYSTEM AND METHOD FOR ROUTING BUS INCLUDING BUFFER 审中-公开
公开(公告)号：US20180113820A1
公开(公告)日：2018-04-26
申请号：US15617117
申请日：2017-06-08
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-yong KIM
IPC分类号： G06F13/16 , G06F13/42 , G06F15/78
CPC分类号： G06F13/1673 , G06F13/1657 , G06F13/4282 , G06F15/7821 , G06F17/5072 , G06F17/5077 , G06F2213/16
摘要： Program procedures executed to rout a bus, via a processing unit, include a bus information extractor configured to extract bus information including physical requirements for the bus, from input data, a buffer array generator configured to generate a buffer array in which buffers included in the bus are regularly arranged based on the bus information, a buffer array placer configured to place at least one buffer array in the layout of the integrated circuit based on the bus information, and a wiring procedure configured to generate interconnections connected to buffers included in the at least one buffer array based on the bus information.

4. 发明申请

US20180067789A1 METHOD FOR PROCESSING VEHICLE-TO-X MESSAGES 审中-公开
公开(公告)号：US20180067789A1
公开(公告)日：2018-03-08
申请号：US15642421
申请日：2017-07-06
申请人： Continental Teves AG & Co. oHG
发明人： Torsten Martin , Marc Menzel , Richard Scherping , Ulrich Stählin
IPC分类号： G06F9/54 , G06F13/16
CPC分类号： G06F9/546 , G06F13/1673 , G06F21/606 , G06F2213/16 , G08G1/161 , G08G1/164 , H04W4/12 , H04W4/40 , H04W12/00 , H04W12/1006 , H04W12/1008
摘要： A method for processing vehicle-to-X messages in a processing module and a method for processing vehicle-to-X messages in a control module. In the course of this messages are checked in a specified checking sequence.

5. 发明授权

US09195621B2 System and method for assigning memory access transfers between communication channels 有权
标题翻译：在通信通道之间分配存储器访问传输的系统和方法
公开(公告)号：US09195621B2
公开(公告)日：2015-11-24
申请号：US13838133
申请日：2013-03-15
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F13/16 , G06F13/28
CPC分类号： G06F13/1631 , G06F13/1647 , G06F13/28 , G06F2213/16 , G06F2213/2806
摘要： A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.
摘要翻译：通信信道控制器包括队列，存储器映射和调度器。存储在通信信道控制器处接收的第一存储器传送请求的队列。存储器映射存储用于标识与存储器相关联的存储器地址范围的信息。调度器将队列中的第一存储器传输的源地址与存储器映射中的存储器地址范围进行比较，以确定第一存储器传送请求的源地址是否针对存储器，并且响应于将第一存储器传送请求分配给多个通信信道的第一通信信道响应于第一通信信道具有其所有未完成的存储器事务到公共源地址组和作为源地址组的源地址页和第一存储器转移请求的源地址页。

6. 发明授权

US09524254B2 Multi-serial interface stacked-die memory architecture 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US09524254B2
公开(公告)日：2016-12-20
申请号：US14456839
申请日：2014-08-11
申请人： Micron Technology, Inc.
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G06F13/00 , G06F13/16 , G06F13/40
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

7. 发明申请

US20140351503A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US20140351503A1
公开(公告)日：2014-11-27
申请号：US14456839
申请日：2014-08-11
申请人： Micron Technology, Inc.
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G06F13/16 , G06F13/40
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

8. 发明授权

US08806152B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
标题翻译：用于通过通信总线从多个源发送数据的方法和装置
公开(公告)号：US08806152B2
公开(公告)日：2014-08-12
申请号：US13692269
申请日：2012-12-03
申请人： Micron Technology, Inc.
发明人： James W. Meyer , Kirsten Renick
IPC分类号： G06F13/16
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.
摘要翻译：在存储器系统中，多个存储器模块通过总线进行通信。每个存储器模块可以包括集线器和至少一个存储器存储单元。集线器从存储器存储单元接收本地数据，并从一个或多个其他存储器模块接收下行数据。集线器汇集通过总线发送的数据，数据块结构分为多个通道。指示在数据块结构内由第一源（例如，本地或下行数据）在总线上的数据中将发生断点的位置。基于指示，来自第二源（例如，下游或本地数据）的数据被放置在数据块的剩余部分中，从而减少总线上的间隙。公开了附加装置，系统和方法。

9. 发明申请

US20110264858A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US20110264858A1
公开(公告)日：2011-10-27
申请号：US13179156
申请日：2011-07-08
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G06F12/08
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

10. 发明授权

US07779212B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
标题翻译：用于通过通信总线从多个源发送数据的方法和装置
公开(公告)号：US07779212B2
公开(公告)日：2010-08-17
申请号：US10688461
申请日：2003-10-17
申请人： James W. Meyer , Kirsten Renick
发明人： James W. Meyer , Kirsten Renick
IPC分类号： G06F12/02
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus.
摘要翻译：在存储器系统中，多个存储器模块通过总线进行通信。每个存储器模块包括集线器和至少一个存储器存储单元。集线器从存储器存储单元接收本地数据，并从一个或多个其他存储器模块接收下行数据。集线器汇集通过总线发送的数据，数据块结构分为多个通道。指示在数据块结构内由第一源（例如，本地或下行数据）在总线上的数据中将发生断点的位置。基于指示，来自第二源（例如，下游或本地数据）的数据被放置在数据块的剩余部分中，从而减少总线上的间隙。

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