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    • 10. 发明申请
    • Combined Binary/Decimal Fixed-Point Multiplier and Method
    • 组合二进制/十进制定点乘数和方法
    • US20100146030A1
    • 2010-06-10
    • US12329686
    • 2008-12-08
    • Mark Alan ErleBrian John Hickmann
    • Mark Alan ErleBrian John Hickmann
    • G06F7/52
    • G06F7/491G06F2207/4915
    • A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations.
    • 使用BCD-4221重新编码为十进制数字的组合二进制/十进制定点乘数。 这允许使用二进制进位保存硬件来执行小数加法与小修正。 所描述的设计提供了改进的减少树组织以减少乘法器的面积和延迟以及利用冗余十进制编码的减少树组件的改进以帮助减少延迟。 还引入了分解还原树架构,减少了二进制产品的延迟,总面积只有小的增加。 提出了区域和延迟估计,表明所提出的设计对于单独的二进制和十进制乘法器具有显着的面积改进,同时对于十进制和二进制运算仍然保持类似的延迟。