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1. 发明申请

US20180300107A1 Energy-Efficient Variable Power Adder and Methods of Use Thereof 审中-公开
公开(公告)号：US20180300107A1
公开(公告)日：2018-10-18
申请号：US15488019
申请日：2017-04-14
申请人： QUALCOMM Incorporated
发明人： Hari Rao
IPC分类号： G06F7/502 , G06F7/505
CPC分类号： G06F7/502 , G06F7/505 , G06F7/506 , G06F2207/5063
摘要： A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

2. 发明授权

US07111034B2 Carry foreknowledge adder 失效
标题翻译：携带预知加法器
公开(公告)号：US07111034B2
公开(公告)日：2006-09-19
申请号：US10352903
申请日：2003-01-29
申请人： Shinichi Ozawa
发明人： Shinichi Ozawa
IPC分类号： G06F7/508
CPC分类号： G06F7/508 , G06F2207/5063
摘要： A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.
摘要翻译：进位预知加法器包括用于加入n位的二进制数A和B的加法电路; 以及分别对应于通过设置单位长度而通过划分A和B获得的分割部分的多个进位预知电路块。每个进位预知电路块具有对应于每个位的多个算术运算部分（j，i），分别在较低的进位预知中分别接收对应于最高有效位的中的块进位C < 电路块与较低分位部分相对应的较低进位预知电路块，每个算术运算部分基于中的块进位C 算术确定进位C i，向加法电路输出进位C i i i，并且每个算术运算部分（j，i）都具有逻辑电路部分，其接收中的块进位C＆amp; 输出端子侧。

3. 发明申请

US20040220993A1 Low power adder 审中-公开
标题翻译：低功率加法器
公开(公告)号：US20040220993A1
公开(公告)日：2004-11-04
申请号：US10425987
申请日：2003-04-30
申请人： Intel Corporation
发明人： Sanu K. Mathew , Mark A. Anders , Ram Krishnamurthy
IPC分类号： G06F007/50
CPC分类号： G06F7/506 , G06F7/507 , G06F7/508 , G06F2207/5063
摘要： Embodiments of the present invention generally relate to an adder. In embodiments, the adder may include two adder circuits which each process a segment of a first number and a second number. The second adder, for processing the higher order digits, may be operated at a lower voltage supply level than the first adder for processing lower order digits. Accordingly, power savings may be accomplished with a nominal time delay penalty.
摘要翻译：本发明的实施例一般涉及加法器。在实施例中，加法器可以包括两个加法器电路，每个加法器电路处理第一号码和第二号码的片段。用于处理较高位数字的第二加法器可以在比用于处理较低位数字的第一加法器更低的电源电平下操作。因此，可以以标称时间延迟罚款来实现功率节省。

4. 发明授权

US06571269B1 Noise-tolerant digital adder circuit and method 失效
标题翻译：耐噪声数字加法器电路及方法
公开(公告)号：US06571269B1
公开(公告)日：2003-05-27
申请号：US09475422
申请日：1999-12-30
申请人： Ram K. Krishnamurthy , Jay R. Anderson
发明人： Ram K. Krishnamurthy , Jay R. Anderson
IPC分类号： G06F750
CPC分类号： G06F7/506 , G06F2207/5063
摘要： A digital adder circuit is implemented using a Kogge-Stone architecture. Various embodiments utilize single-ended domino circuits, to which are input single-ended primary addends. Dual-function generator circuits generate differential sum and sum-complement output signals. The use of low VT devices and full CMOS circuitry provides a relatively high degree of noise immunity. Also described are a microprocessor having an ALU incorporating one or more of the adder circuits, as well as a method of adding two numbers which generates differential sum and sum-complement outputs but does not use full-differential domino circuits, thus providing considerable savings in circuit area, circuit conductors, and layout complexity.
摘要翻译：数字加法器电路使用Kogge-Stone架构实现。各种实施例使用单端多米诺骨牌电路，输入单端主增加器。双功能发生器电路产生微分和和和补和输出信号。使用低VT器件和全CMOS电路提供相对较高的抗噪声能力。还描述了一种具有并入一个或多个加法器电路的ALU的微处理器，以及一种相加两个产生微分和和和补和输出但不使用全差分多米诺骨电路的数字的方法，电路面积，电路导体和布局复杂度。

5. 发明授权

US5777491A High-performance differential cascode voltage switch with pass gate logic elements 失效
标题翻译：具有通过门逻辑元件的高性能差分共源共栅电压开关
公开(公告)号：US5777491A
公开(公告)日：1998-07-07
申请号：US660836
申请日：1996-06-10
申请人： Wei Hwang , Fang-Shi Jordan Lai
发明人： Wei Hwang , Fang-Shi Jordan Lai
IPC分类号： G06F7/50 , G06F7/508 , H03K19/173 , H03K19/0948
CPC分类号： G06F7/508 , H03K19/1738 , G06F2207/5063
摘要： Performance of a dual cascode voltage switch is improved and floating node effects including charge sharing and ratioing of output voltages are avoided by constituting the true and complement logic trees as pass gates of equal height, preferably limited, where possible, to a single transistor. The logic trees have substantially identical transistor layout configurations and different logic functions are established by selective connection of control and conduction terminals of the pass gates to reference logic level voltages of true and complement input variable signal values.
摘要翻译：改进了双共源共栅电压开关的性能，并且通过将真实和补码逻辑树构成相等高度的通孔来避免包括电荷共享和输出电压的比例的浮动节点效应，在可能的情况下，优选地限于单个晶体管。逻辑树具有基本上相同的晶体管布局配置，并且通过将通孔的控制和导通端子选择性地连接到真实和补码输入可变信号值的参考逻辑电平电压来建立不同的逻辑功能。

6. 发明授权

US5689451A Device for calculating parity bits associated with a sum of two numbers 失效
标题翻译：用于计算与两个数字的和相关联的奇偶校验位的设备
公开(公告)号：US5689451A
公开(公告)日：1997-11-18
申请号：US714486
申请日：1996-09-16
申请人： Pascal Delamotte , Michel Thill
发明人： Pascal Delamotte , Michel Thill
IPC分类号： G06F7/38 , G06F7/50 , G06F7/508 , G06F11/10 , H03M13/09 , G06F11/00
CPC分类号： G06F7/508 , G06F11/10 , H03M13/09 , H03M13/098 , G06F2207/5063
摘要： In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two numbers A and B and the result S. Each number A and B and the result S is divided into K groups each of m bits, and one parity bit is associated with each group. In accordance with the invention, the parity PS associated with the result S is obtained at the same time as the result. The input carry bit c.sub.i n intervening in the addition is available before the beginning of operations. Consequently, it is used in a first stage 10' upstream of the device, which calculates intermediate variables p.sub.i,j and g.sub.i,j. The other input carry bits c.sub.i,1 corresponding to the other groups are determined only later by a carry look ahead circuit, and consequently they are used only in a second stage 50' downstream of the device. The use of c.sub.i n in the first stage 10' makes it possible to perform the calculation of the parity bits and look ahead for the carry bits with a single circuit present in a third stage 60, which is intermediate between the first stage 10' and the second stage 50'.
摘要翻译：在找到两个二进制数A和B的和的加法器中，现在常规的是将一个或多个奇偶校验位（PA，PB，PS）与两个数字A和B中的每一个以及结果S相关联。每个数字A 和B，并且将结果S划分成每个m位的K个组，并且一个奇偶校验位与每个组相关联。根据本发明，与结果S同时获得与结果S相关联的奇偶校验PS。插入的输入进位位cin在开始操作之前可用。因此，它被用于器件上游的第一级10'，它计算中间变量pi，j和gi，j。仅与稍后通过进位查看电路确定对应于其他组的其他输入进位位ci，1，因此它们仅在设备下游的第二级50'中使用。在第一级10'中使用cin使得可以执行奇偶校验位的计算，并且使用第三级60中存在的单个电路来查看进位位，第三级60位于第一级10'和第二阶段50'。

7. 发明授权

US5631860A Carry Selecting system type adder 失效
标题翻译：进位选择系统类型加法器
公开(公告)号：US5631860A
公开(公告)日：1997-05-20
申请号：US461011
申请日：1995-06-05
申请人： Hiroyuki Morinaka
发明人： Hiroyuki Morinaka
IPC分类号： G06F7/50 , G06F7/507 , G06F7/508
CPC分类号： G06F7/508 , G06F7/507 , G06F2207/5063
摘要： An adder including a first exclusive OR device, a second exclusive OR device for receiving an output of the first exclusive OR device and a generating signal G(i-1), exclusive ORing the output result of the first exclusive OR device and the generating signal G(i-1), and outputting the calculated result as a sum Si0, and a third exclusive OR device for receiving an output of the second exclusive OR device and a propagating signal P(i-1), exclusive ORing the output result of the second exclusive OR device and the propagating signal P(i-1), and outputting the calculated result as a sum Si1, whereby the amount of hardware and power consumption of the adder used in a carry selecting system is reduced.
摘要翻译：一种加法器，包括第一异或装置，用于接收第一异或装置的输出的第二异或装置和产生信号G（i-1），将第一异或装置的输出结果与产生信号 G（i-1），并将计算结果作为和Si0输出;以及第三异或装置，用于接收第二异或装置的输出和传播信号P（i-1）第二异或装置和传播信号P（i-1），并将计算结果输出为和Si1，从而减少进位选择系统中使用的加法器的硬件和功耗。

8. 发明授权

US5166899A Lookahead adder 失效
标题翻译： LOOKAHEAD ADDER
公开(公告)号：US5166899A
公开(公告)日：1992-11-24
申请号：US554612
申请日：1990-07-18
申请人： Joel D. Lamb
发明人： Joel D. Lamb
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/5063
摘要： In a lookahead adder of the type wherein carry signals for successive stages of the adder are derived by a pyramid of hierarchically-arranged logic circuits, supplemented by carry signals from intermediate ones of the adder stages. The need to rely on such intermediate carry signals is dispensed with by additional non-hierarchically-arranged logic circuits whose outputs provide the information previously derived from intermediate carry outputs.

9. 发明授权

US5122982A Carry generation method and apparatus 失效
标题翻译：携带生成方法和装置
公开(公告)号：US5122982A
公开(公告)日：1992-06-16
申请号：US619741
申请日：1990-10-17
申请人： Leonard A. Cohn
发明人： Leonard A. Cohn
IPC分类号： G06F7/50 , G06F7/506
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/5063
摘要： Methods and apparatus for digital addition are disclosed in particular methods and apparatus for "carrying" in digital addition, and methods for designed carry circuits using circle and tally diagrams. A general method for creating and analyzing carry circuits is developed which not only permits the analysis of existing carry circuits such as those of the ripple-carry adder and the carry look-ahead adder; but also leads to new faster carry circuits.
摘要翻译：用于数字加法的方法和装置在数字加法中“携带”的具体方法和装置以及使用圆和图表的设计的进位电路的方法中公开。开发了一种用于创建和分析进位电路的一般方法，它不仅可以分析现有的进位电路，如纹波进位加法器和进位查找加法器; 而且还带来了更快的携带电路。

10. 发明授权

US11662979B2 Adder circuitry for very large integers 有权
公开(公告)号：US11662979B2
公开(公告)日：2023-05-30
申请号：US16953135
申请日：2020-11-19
申请人： Intel Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/506 , G06F7/505 , G06F7/503 , G06F17/16 , H03K19/173 , H03K19/17724 , H03K19/17736
CPC分类号： G06F7/506 , G06F7/503 , G06F7/505 , G06F17/16 , H03K19/1737 , H03K19/17724 , H03K19/17744 , G06F2207/4812 , G06F2207/5063
摘要： An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

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