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1. 发明授权

US08099447B2 Negative two's complement processor for windowing in harmonic analysis 失效
标题翻译：负二阶补码处理器用于窗口谐波分析
公开(公告)号：US08099447B2
公开(公告)日：2012-01-17
申请号：US12925352
申请日：2010-10-20
申请人： Earl Eugene Swartzlander, Jr.
发明人： Earl Eugene Swartzlander, Jr.
IPC分类号： G06F15/00 , G06F7/52
CPC分类号： G06F7/38 , G06F7/4991 , G06F7/53 , G06F7/5336 , G06F2207/3832
摘要： The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, an−1, and n−1 fractional bits, an−2, an−3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ∑ i = 0 n - 2 ⁢ - a i ⁢ 2 i - n + 1 .
摘要翻译：本发明提供了一种常规用于现代计算系统和数字信号处理器的传统二进制补码系统的缺点的解决方案，用于计算使用离散时频变换的谐波分析。在负二进制补码处理器中，n位数字A具有符号位，1和1分数位，a-2，a-3。。。，a0。 n位分数负二进制补码的值为：A = a n-1 +Σi = 0 n - 2 - a i 2 i - n + 1。

2. 发明授权

US07805478B2 Montgomery modular multiplier 有权
标题翻译：蒙哥马利模块乘法器
公开(公告)号：US07805478B2
公开(公告)日：2010-09-28
申请号：US11068371
申请日：2005-03-01
申请人： Hee-Kwan Son
发明人： Hee-Kwan Son
IPC分类号： G06F7/38 , H04K1/00
CPC分类号： G06F7/728 , G06F7/5336
摘要： In a Montgomery multiplier, a modulus product generator may select a modulus product from a plurality of selectable n-bit modulus numbers M, a given modulus number M being formed from a currently input extended chunk of bits among the n-bit modulus numbers. A partial product generator may select a multiplicand number from a plurality of selectable n-bit multiplicands A as a partial product, a given multiplicand A being formed from a currently input extended chunk of bits among the n-bit multiplicands. An accumulator may accumulate the selected modulus product and partial product to generate a multiplication result. The Montgomery multiplier may be part of an operation unit that may include a memory and host, and may be adapted to perform a Montgomery multiplication operation and a normal multiplication operation based on a logic state of a control signal input thereto.
摘要翻译：在蒙哥马利倍增器中，模量乘积发生器可以从多个可选择的n位模数M中选择模量乘积，给定的模数M由n位模数中的当前输入的扩展块组成。部分乘积生成器可以从多个可选择的n比特被乘数A中选择被乘数作为部分乘积，给定的被乘数A由n比特被乘数中的当前输入的扩展块组成。累加器可以累积所选择的模量积和部分乘积以产生乘法结果。蒙哥马利乘法器可以是可以包括存储器和主机的操作单元的一部分，并且可以适于基于输入到其的控制信号的逻辑状态执行蒙哥马利乘法运算和正常乘法运算。

3. 发明授权

US07174015B1 Methods and apparatus for variable radix scalable modular multiplication 失效
标题翻译：用于可变基数可扩展模数乘法的方法和装置
公开(公告)号：US07174015B1
公开(公告)日：2007-02-06
申请号：US10134045
申请日：2002-04-25
申请人： Çetin K. Koç , Alexandre F. Tenca , Georgi Todorov
发明人： Çetin K. Koç , Alexandre F. Tenca , Georgi Todorov
IPC分类号： H04L9/06 , H04L9/34 , H04L9/18
CPC分类号： G06F7/728 , G06F7/5336
摘要： Methods and apparatus for Montgomery multiplication process a multiplier operand in k-bit radix-digits, wherein k corresponds to a radix r=2k. A multiplicand operand and a modulus are processed word by word, and then additional bits of the multiplier operand are selected for processing. In a radix r=8 example, the multiplier operand is processed in 3 bit radix-8 digits. A processing kernel is configured to preprocess the modulus and/or the multiplier operand so that at least some values can be obtained from lookup tables.
摘要翻译：用于蒙哥马利乘法的方法和装置在k位基数中处理乘法器操作数，其中k对应于基数r = 2K。被乘数操作数和模数逐字进行处理，然后选择乘法器操作数的附加位进行处理。在radix r = 8的例子中，乘法器操作数以3位8进制数字处理。处理内核被配置为预处理模数和/或乘数操作数，使得可以从查找表获得至少一些值。

4. 发明申请

US20060008080A1 Modular-multiplication computing unit and information processing unit 审中-公开
标题翻译：模块化乘法运算单元和信息处理单元
公开(公告)号：US20060008080A1
公开(公告)日：2006-01-12
申请号：US11176209
申请日：2005-07-08
申请人： Kunihiko Higashi , Toru Hisakado , Satoshi Goto , Takeshi Ikenaga
发明人： Kunihiko Higashi , Toru Hisakado , Satoshi Goto , Takeshi Ikenaga
IPC分类号： H04K1/00
CPC分类号： G06F7/728 , G06F7/5336
摘要： The bit strings of multipliers B and N are converted through the use of the Booth's algorithm in units composed of a predetermined number of bits and the operation of A×B+u×N is executed by a carry save adder using the value of an integral multiple of multiplicand A corresponding to the multiplication result of the values of the converted multiplier B and multiplicand A and also the value of an integral multiple of multiplicand u corresponding to the multiplication result of the values of the converted multiplier N and multiplicand u. The operation result of A×B+u×N supplied from the carry save adder are added to the operation result in the past of A×B+u×N through the use of an adder and the added result is supplied as the result of a modular-multiplication operation S=S+A×B+u×N.
摘要翻译：乘法器B和N的位串通过使用布斯算法以由预定位数组成的单位进行转换，并且通过进位保存加法器执行AxB + uxN的操作，使用被乘数A的整数倍的值对应于转换乘法器B和被乘数A的值的乘法结果，以及与转换乘法器N和被乘数u的值的相乘结果相对应的乘法u的整数倍的值。由进位保存加法器提供的AxB + uxN的运算结果通过使用加法器在AxB + uxN过去加到运算结果中，相加结果作为乘法运算的结果S = S + AxB + uxN。

5. 发明申请

US20050223054A1 Multiplier sign extension method and architecture 审中-公开
标题翻译：乘法符号扩展方法和架构
公开(公告)号：US20050223054A1
公开(公告)日：2005-10-06
申请号：US10893226
申请日：2004-07-19
申请人： Yu-Cheng Lo
发明人： Yu-Cheng Lo
IPC分类号： G06F7/499 , G06F7/52 , G06F7/533
CPC分类号： G06F7/49994 , G06F7/5336
摘要： A multiplier sign extension method and architecture are used for encoding operations of a multiplier of a digital signal processor. The multiplier sign extension method comprises the steps of: determining the width of the multiplier to obtain a sign extension bit total value; encoding a multiplier by means of the modified Booth algorithm; calculating out a plurality of layers of partial product terms by multiplying a multiplicand by the encoded multiplier to form a first stepwise bit table; setting a plurality of complementary bits, a first correction bit and a second correction bit to form a second stepwise bit table; and summing up the plurality of layers of the second stepwise bit table. Without increasing critical paths, a plurality of complementary bits is provided for encoding of sign extension to reduce waste of chip area and make the multiplier smaller.
摘要翻译：乘法器符号扩展方法和架构用于数字信号处理器的乘法器的编码操作。乘法器符号扩展方法包括以下步骤：确定乘法器的宽度以获得符号扩展位总值; 通过改进的布斯算法对乘数进行编码; 通过将被乘数乘以编码乘数来计算多个部分乘积项的层以形成第一逐步位表; 设置多个互补位，第一校正位和第二校正位，以形成第二逐步位表; 并且对第二阶梯位表的多个层进行求和。在不增加关键路径的情况下，提供多个互补位用于对符号扩展进行编码以减少芯片面积的浪费，并使乘法器更小。

6. 发明申请

US20050198093A1 Montgomery modular multiplier 有权
标题翻译：蒙哥马利模块乘法器
公开(公告)号：US20050198093A1
公开(公告)日：2005-09-08
申请号：US11068371
申请日：2005-03-01
申请人： Hee-Kwan Son
发明人： Hee-Kwan Son
IPC分类号： G06F7/72 , G06F7/38 , G06F7/44 , G06F7/52 , G06F7/533 , G06F15/00 , G09C1/00
CPC分类号： G06F7/728 , G06F7/5336
摘要： In a Montgomery multiplier, a modulus product generator may select a modulus product from a plurality of selectable n-bit modulus numbers M, a given modulus number M being formed from a currently input extended chunk of bits among the n-bit modulus numbers. A partial product generator may select a multiplicand number from a plurality of selectable n-bit multiplicands A as a partial product, a given multiplicand A being formed from a currently input extended chunk of bits among the n-bit multiplicands. An accumulator may accumulate the selected modulus product and partial product to generate a multiplication result. The Montgomery multiplier may be part of an operation unit that may include a memory and host, and may be adapted to perform a Montgomery multiplication operation and a normal multiplication operation based on a logic state of a control signal input thereto.
摘要翻译：在蒙哥马利倍增器中，模量乘积发生器可以从多个可选择的n位模数M中选择模量乘积，给定的模数M由n位模数中的当前输入的扩展块组成。部分乘积生成器可以从多个可选择的n比特被乘数A中选择被乘数作为部分乘积，给定的被乘数A由n比特被乘数中的当前输入的扩展块组成。累加器可以累积所选择的模量积和部分乘积以产生乘法结果。蒙哥马利乘法器可以是可以包括存储器和主机的操作单元的一部分，并且可以适于基于输入到其的控制信号的逻辑状态执行蒙哥马利乘法运算和正常乘法运算。

7. 发明申请

US20050125478A1 Smaller and lower power static mux circuitry in generating multiplier partial product signals 有权
标题翻译：产生乘法器部分乘积信号的较小和较低功率的静态多路复用电路
公开(公告)号：US20050125478A1
公开(公告)日：2005-06-09
申请号：US10728395
申请日：2003-12-05
申请人： Kenneth Ng
发明人： Kenneth Ng
IPC分类号： G06F7/52 , G06F7/533
CPC分类号： G06F7/5336
摘要： A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs select Booth-multiply functions. The circuit also includes a plurality of multiplexer circuits, one multiplexer circuit for each bit of the multiplicand. The at least one of the plurality multiplexer circuits includes four pass gates coupled to receive a multiplicand bit, a complement of the multiplicand bit, multiplexed data from a next lower order multiplexer circuit and the encoded outputs of the Booth encoder circuit outputs to provide one bit of a partial product at a multiplexer output.
摘要翻译：用于接收乘法器和被乘数的乘法器电路包括至少一个布斯编码器电路，以将多个乘法器比特编码为四个编码输出。编码输出选择展位乘法功能。该电路还包括多个多路复用器电路，一个用于被乘数的每一比特的多路复用器电路。多个多路复用器电路中的至少一个包括四个通路，其耦合以接收被乘数位，被乘数位的补码，来自下一个较低阶多路复用器电路的多路复用数据和布斯编码器电路输出的编码输出，以提供一位在多路复用器输出处的部分乘积。

8. 发明授权

US5862059A Table compression using bipartite tables 失效
标题翻译：表压缩使用二分表
公开(公告)号：US5862059A
公开(公告)日：1999-01-19
申请号：US504279
申请日：1995-07-19
申请人： David William Matula , Debjit Das Sarma
发明人： David William Matula , Debjit Das Sarma
IPC分类号： G06F1/035 , G06F7/48 , G06F7/52 , G06F7/533 , G06F1/02
CPC分类号： G06F7/4824 , G06F1/0356 , G06F2101/08 , G06F2101/12 , G06F7/5336 , G06F7/5338
摘要： A bipartite compression technique is used to implement a bipartite reciprocal table that provides seed reciprocal values for multiplicative (reciprocal refinement) division. The bipartite reciprocal table (12) includes component tables P and N. The input table index is partitioned into high, middle, and low order parts �x.sub.h .vertline.x.sub.m .vertline.x.sub.1 !'the high and middle order parts �x.sub.h .vertline.x.sub.m ! index the P Table, and the high and low order parts �x.sub.h .vertline.x.sub.1 ! index the N Table. The P and N Tables provide first and second component outputs which form a redundant output from the bipartite lookup table. The bipartite table output may be (a) optimal in that, for each entry in each table, the maximum relative error is the minimum possible, and/or (b) when fused with rounding, faithful (i.e., accurate to one unit in the last place). In an exemplary implementation, the bipartite reciprocal table is used in combination with a Booth recoded multiplier --the redundant borrow-save output from the bipartite table is input directly to the Booth recoder, such that the Booth recoder performs a fusion of the first and second component outputs.
摘要翻译：一种二分压缩技术用于实现一个双向互逆表，它为乘法（相互关联的细化）划分提供了种子互逆值。二分互易表（12）包括分量表P和N.输入表索引被划分为高，中，低阶部分[xh | xm | x1]'，高阶中间部分[xh | xm] P表，高阶和低阶部分[xh | x1]索引N表。 P和N表提供第一和第二分量输出，形成来自二分查找表的冗余输出。二分表输出可以是（a）最优的是，对于每个表中的每个条目，最大相对误差是可能的最小值，和/或（b）当与四舍五入，忠实（即精确到一个单位在最后一个地方）。在示例性实施方式中，二分互易表与布斯重编号乘法器组合使用 - 来自二分表的冗余借位保存输出被直接输入到布斯重新编码器，使得布斯记录器执行第一和第二组件输出。

9. 发明授权

US5337268A Partial multiplier selector for multiplication circuit 失效
标题翻译：用于乘法电路的部分乘法器选择器
公开(公告)号：US5337268A
公开(公告)日：1994-08-09
申请号：US940318
申请日：1992-09-03
申请人： Shingo Kojima
发明人： Shingo Kojima
IPC分类号： G06F7/00 , G06F7/52 , G06F7/523 , G06F7/533
CPC分类号： G06F7/5336
摘要： The present invention simplifies a partial multiplier selector for a multiplication circuit using the Booth Algorithm. For this purpose, a partial multiplier selector according to the present invention comprises a multiplier register to store multiplier data, a plurality of partial multiplier selecting units comprising clocked inverters which divide the multiplier data stored in the multiplier register using the multiplication start signal and sequentially fetch them and control circuits comprising latch circuits which sequentially output the multiplication start signal to the partial multiplier selecting units with a delay of one clock using the clock signal.
摘要翻译：本发明简化了使用布斯算法的乘法电路的部分乘法器选择器。为此，根据本发明的部分倍增器选择器包括：乘法器寄存器，用于存储乘法器数据;多个部分乘法器选择单元，包括时钟反相器，其使用乘法开始信号对存储在乘法器寄存器中的乘法器数据进行分频，它们和控制电路包括使用时钟信号以一个时钟的延迟顺序地将乘法开始信号输出到部分乘法器选择单元的锁存电路。

10. 发明授权

US4965762A Mixed size radix recoded multiplier 失效
标题翻译：混合大小的基数重新编码乘数
公开(公告)号：US4965762A
公开(公告)日：1990-10-23
申请号：US407828
申请日：1989-09-15
申请人： Tim A. Williams
发明人： Tim A. Williams
IPC分类号： G06F7/52
CPC分类号： G06F7/5336
摘要： An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm. In order to avoid delaying the computation of partial products until after the time special products are formed, two recoding radices may be used. Partial products can be calculated from terms formed by a smaller sized radix during the same time the special product terms are being calculated. Initial use of the smaller radix eliminates an immediate need for the special product bits which improves multiplier speed by minimizing time required to form a final product.
摘要翻译：利用预定的重新编码算法的阵列乘法器通过使用两个不同的天线来最小化操作速度。必须形成特殊的产品术语来实现记录算法。为了避免延迟部分产品的计算，直到形成特殊产品为止，可以使用两个记录基准。部分产品可以在计算特殊产品术语的同时由较小尺寸的基数形成的术语计算。初始使用较小的基数消除了特殊产品位的迫切需求，通过最小化形成最终产品所需的时间来提高乘数速度。

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