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1. 发明申请

US20190243739A1 TIME SERIES RETRIEVAL FOR ANALYZING AND CORRECTING SYSTEM STATUS 审中-公开
公开(公告)号：US20190243739A1
公开(公告)日：2019-08-08
申请号：US16245740
申请日：2019-01-11
申请人： NEC Laboratories America, Inc.
发明人： Dongjin Song , Ning Xia , Haifeng Chen
IPC分类号： G06F11/34 , G06F11/07 , G06F11/28 , G06F16/2457 , G06N3/02 , G06N7/08
CPC分类号： G06F11/3452 , G06F11/0793 , G06F11/28 , G06F11/3419 , G06F16/24578 , G06N3/02 , G06N7/08
摘要： Methods and systems for detecting and correcting anomalous behavior include generating a joint binary embedding of each of a set of historical time series sequences. A joint binary embedding of a recent time series sequence is generated. A ranked list of the plurality of historical time series sequences is generated according to respective similarities of each historical time series sequence to the recent time series sequence based on the respective joint binary embeddings of each. Anomalous behavior of a system associated with the recent time series sequence is determined according to a label of a top-ranked historical time series sequence in the ranked list. A corrective action is performed to correct the anomalous behavior.

2. 发明申请

US20180269897A1 NON-BINARY CONTEXT MIXING COMPRESSOR/DECOMPRESSOR 审中-公开
公开(公告)号：US20180269897A1
公开(公告)日：2018-09-20
申请号：US15458651
申请日：2017-03-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： TOBIAS BLAETTLER , THOMAS MITTELHOLZER , THOMAS PARNELL , CHARALAMPOS POZIDIS
IPC分类号： H03M7/30 , G06N99/00 , G06N7/08 , G06N3/04 , G06N3/08
CPC分类号： H03M7/30 , G06N3/04 , G06N3/08 , G06N5/046 , G06N7/08 , G06N20/00 , H03M7/3079 , H03M7/4018 , H04N19/13 , H04N19/91
摘要： A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

3. 发明申请

US20180246393A1 ISING MODEL QUANTUM COMPUTATION DEVICE 审中-公开
公开(公告)号：US20180246393A1
公开(公告)日：2018-08-30
申请号：US15758536
申请日：2016-09-14
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION , Inter-University Research Institute Corporation Research Organization of Information and Systems , OSAKA UNIVERSITY
发明人： Takahiro INAGAKI , Hiroki TAKESUE , Toshimori HONJO , Shoko UTSUNOMIYA , Yoshihisa YAMAMOTO , Yoshitaka HARIBARA , Shuhei TAMATE , Koji IGARASHI
IPC分类号： G02F1/39 , G02F3/00 , G06N7/08 , G06N99/00
CPC分类号： G02F1/39 , G02F3/00 , G06N5/003 , G06N7/08 , G06N99/002
摘要： In an Ising spin measuring step, measurement is suspended after one set of measurement of all Ising spins {σi} is completed before another set of measurement of all Ising spins {σi} is restarted. In an Ising interaction computing step, all Ising interactions relating to all the Ising spins σi can be computed with a sufficient time margin on the basis of most recent measurement of Ising spins σi, after one set of measurement of all the Ising spins {σi} is completed before another set of measurement of all the Ising spins {σi} is restarted by the Ising spin measuring step.

4. 发明申请

US20180212752A1 End-To-End Secure Operations from a Natural Language Expression 审中-公开
公开(公告)号：US20180212752A1
公开(公告)日：2018-07-26
申请号：US15875933
申请日：2018-01-19
申请人： Enveil, Inc.
发明人： Ellison Anne Williams , Ryan Carr
IPC分类号： H04L9/00 , G06F17/27 , G06F17/30 , H04L9/14 , H04L29/06 , H04L9/30
CPC分类号： H04L9/008 , G06F16/254 , G06F16/3344 , G06F17/16 , G06F17/271 , G06F17/274 , G06F17/277 , G06F17/278 , G06F17/2785 , G06F21/30 , G06F21/6218 , G06N3/04 , G06N3/08 , G06N7/08 , G09C1/00 , H04L9/0643 , H04L9/0861 , H04L9/14 , H04L9/30 , H04L9/302 , H04L9/3242 , H04L63/0435 , H04L2209/04 , H04L2209/12
摘要： Systems and methods for an end-to-end secure operation from an expression in natural language. Exemplary methods include: receiving a set of queries from a natural language processor, the set of queries being produced by a method including: getting data schemas associated with a target data source; obtaining the expression in natural language; performing natural language processing on the expression to determine a desired operation; and generating the set of queries using at least one of matching and inference techniques over the desired operation with respect to the data schemas; encrypting the set of queries using a homomorphic encryption technique; providing the encrypted set of queries to a server, the server including the target data source; acquiring encrypted results, the encrypted results being responsive to the encrypted set of queries; and decrypting the encrypted results using a decryption key to produce desired results.

5. 发明申请

US20170147946A1 METHOD AND APPARATUS FOR MACHINE LEARNING 审中-公开
公开(公告)号：US20170147946A1
公开(公告)日：2017-05-25
申请号：US15334405
申请日：2016-10-26
申请人： FUJITSU LIMITED
发明人： YUHEI UMEDA
IPC分类号： G06N99/00 , G06N5/04
CPC分类号： G06N20/00 , G06N5/046 , G06N7/08
摘要： A machine learning method related to these embodiments includes: first generating a pseudo attractor from each of plural series data sets, the pseudo attractor being a set of points in N-dimensional space, each of the points including N values sampled at an equal interval; second generating a series data set of Betti numbers from each of plural pseudo attractors generated in the first generating, each of the Betti numbers being a number of holes for a radius of a N-dimensional sphere in the N-dimensional space; and performing machine learning for each of plural series data sets of Betti numbers generated in the second generating, the series data set of Betti numbers being used as input in the machine learning.

6. 发明申请

US20160162799A1 COUPLING OF RATIONAL AGENTS TO QUANTUM PROCESSES 审中-公开
标题翻译：与量子过程耦合
公开(公告)号：US20160162799A1
公开(公告)日：2016-06-09
申请号：US14931747
申请日：2015-11-03
申请人： MIND OVER MATTER AI, LLC.
发明人： Michael Levin
IPC分类号： G06N99/00 , G06N7/08
CPC分类号： G06N10/00 , B82Y10/00 , G06N7/08
摘要： The present invention provides devices, methods, and systems for coupling a rational agent to a quantum process. In particular, the present invention provides rational agents configured to influence a quantum process, or to derive information from a quantum process, and methods and uses thereof
摘要翻译：本发明提供了用于将理性剂耦合到量子过程的装置，方法和系统。特别地，本发明提供了被配置为影响量子过程或从量子过程导出信息的有理代理及其方法和用途

7. 发明授权

US08620631B2 Method of identifying Hammerstein models with known nonlinearity structures using particle swarm optimization 失效
标题翻译：使用粒子群优化识别具有已知非线性结构的Hammerstein模型的方法
公开(公告)号：US08620631B2
公开(公告)日：2013-12-31
申请号：US13084429
申请日：2011-04-11
申请人： Hussain N. Al-Duwaish
发明人： Hussain N. Al-Duwaish
IPC分类号： G06F7/60 , G06F17/10 , G06F17/11
CPC分类号： G06N7/08 , G06F17/5009 , G06F2217/16
摘要： The method of identifying Hammerstein models with known nonlinearity structures using particle swarm optimization provides a computerized method utilizing a particle swarm optimization (PSO)-based scheme for the identification of nonlinear Hammerstein models with known nonlinearity structures. Particularly, this is accomplished by formulating the identification of the Hammerstein model as an optimization problem, with PSO being used in the optimization process.
摘要翻译：使用粒子群优化识别具有已知非线性结构的Hammerstein模型的方法提供了利用基于粒子群优化（PSO）的方案来识别具有已知非线性结构的非线性Hammerstein模型的计算机化方法。特别地，这是通过将Hammerstein模型的识别作为优化问题来实现的，其中在优化过程中使用PSO。

8. 发明授权

US08091062B2 Logic circuits having dynamically configurable logic gate arrays 有权
标题翻译：逻辑电路具有动态可配置的逻辑门阵列
公开(公告)号：US08091062B2
公开(公告)日：2012-01-03
申请号：US12174332
申请日：2008-07-16
申请人： William L. Ditto , Krishnamurthy Murali , Sudeshna Sinha
发明人： William L. Ditto , Krishnamurthy Murali , Sudeshna Sinha
IPC分类号： G06F17/50
CPC分类号： G06N7/08
摘要： A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
摘要翻译：提供了一种用于实现逻辑表达式的逻辑门阵列。阵列包括具有混沌更新器的动态可配置逻辑门，用于使逻辑门交替地作为几种不同的逻辑门类型之一交替工作，动态可配置的逻辑门交替地作为一个逻辑门类型操作到不同的逻辑门类型响应于一个或多个参考信号。该阵列还包括一个或多个附加逻辑门。

9. 发明授权

US07925814B2 Dynamically configurable high speed interconnect using a nonlinear element 有权
标题翻译：使用非线性元件的动态配置高速互连
公开(公告)号：US07925814B2
公开(公告)日：2011-04-12
申请号：US12599206
申请日：2008-05-08
申请人： Robert A. Schneiderwind
发明人： Robert A. Schneiderwind
IPC分类号： G06F13/36 , H03K19/177
CPC分类号： H03K19/1733 , G06N7/08
摘要： A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.
摘要翻译：动态可配置的逻辑门包括用于接收第一输入信号的输入加法器和用于产生求和的输入信号的第二输入信号。此外，动态可配置逻辑门包括非线性元件，其将非线性函数应用于求和的输入信号以产生非线性输出信号。响应于调整相加的输入信号和/或非线性函数，可动态配置的逻辑门输出信号对应于多个不同逻辑门中的一个。在另一个实施例中，动态可配置的逻辑门包括对其中一个输入的反馈。动态可配置的逻辑门接收两个输入并且作为多个不同的逻辑门类型之一进行操作，以根据控制信号的选择产生对应于存储器锁存器的输出信号。还公开了可动态配置的逻辑元件的阵列结构。

10. 发明申请

US20080278196A1 LOGIC CIRCUITS HAVING DYNAMICALLY CONFIGURABLE LOGIC GATE ARRAYS 有权
标题翻译：具有动态可配置逻辑门阵列的逻辑电路
公开(公告)号：US20080278196A1
公开(公告)日：2008-11-13
申请号：US12174332
申请日：2008-07-16
申请人： WILLIAM L. DITTO , KRISHNAMURTHY MURALI , SUDESHNA SINHA
发明人： WILLIAM L. DITTO , KRISHNAMURTHY MURALI , SUDESHNA SINHA
IPC分类号： H03K19/173 , H03K19/20
CPC分类号： G06N7/08
摘要： A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
摘要翻译：提供了一种用于实现逻辑表达式的逻辑门阵列。阵列包括具有混沌更新器的动态可配置逻辑门，用于使逻辑门交替地作为几种不同的逻辑门类型之一交替工作，动态可配置的逻辑门从一个逻辑门类型转换为不同的逻辑门类型响应于一个或多个参考信号。该阵列还包括一个或多个附加逻辑门。

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