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1. 发明申请

US20180330767A1 BANK TO BANK DATA TRANSFER 审中-公开
公开(公告)号：US20180330767A1
公开(公告)日：2018-11-15
申请号：US15595171
申请日：2017-05-15
申请人： Micron Technology, Inc.
发明人： Perry V. Lea , Troy A. Manning
IPC分类号： G11C7/10 , H03K19/173 , G06F13/12 , G06F12/02 , G06F3/06
CPC分类号： G11C7/1006 , G06F3/0683 , G06F12/02 , G06F12/0238 , G06F13/124 , G06F2003/0692 , H03K19/1733
摘要： The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

2. 发明授权

US09997214B1 LevelShifter-less output buffer with hybrid driver for high speed and low supply memory applications 有权
公开(公告)号：US09997214B1
公开(公告)日：2018-06-12
申请号：US15637711
申请日：2017-06-29
申请人： Cadence Design Systems, Inc.
发明人： Vinod Kumar , Tara Vishin
IPC分类号： G11C7/00 , G11C7/10 , G11C14/00 , G11C5/14 , G11C11/40 , H03K19/173 , H03K19/00 , H03K19/0185
CPC分类号： G11C7/1057 , G11C5/145 , G11C5/147 , G11C7/1069 , G11C11/40 , G11C11/4074 , G11C11/4093 , G11C11/4096 , G11C14/0009 , G11C2207/105 , H03K19/00 , H03K19/0005 , H03K19/0185 , H03K19/018521 , H03K19/173 , H03K19/1733
摘要： Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

3. 发明申请

US20180159538A1 SYSTEM RELATED INTEGRATED CIRCUIT, APPARATUS AND METHOD 审中-公开
公开(公告)号：US20180159538A1
公开(公告)日：2018-06-07
申请号：US15607588
申请日：2017-05-29
申请人： STMicroelectronics S.r.l.
发明人： Francesco Pappalardo , Giuseppe Notarangelo
IPC分类号： H03K19/21
CPC分类号： H03K19/21 , G08C2201/91 , H03K19/1733 , H03K19/1737 , H03K2217/94021 , H04L61/2038 , H04L61/6072
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

4. 发明申请

US20180159537A1 PROGRAMMABLE STRUCTURED ARRAYS 审中-公开
公开(公告)号：US20180159537A1
公开(公告)日：2018-06-07
申请号：US15877224
申请日：2018-01-22
申请人： CALLAHAN CELLULAR L.L.C.
发明人： Raminda Udaya Madurawe
IPC分类号： H03K19/173 , H03K19/177 , H01L23/525 , H01L27/02 , H01L27/11 , H01L27/118 , H01L27/12 , H01L27/06 , H01L27/105 , H01L27/108
CPC分类号： H03K19/1735 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L27/11803 , H01L27/11898 , H01L27/1203 , H01L2924/0002 , H03K19/1733 , H03K19/17728 , H03K19/1776 , H01L2924/00
摘要： A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

5. 发明申请

US20180091155A1 PROGRAMMABLE LOGIC CIRCUIT AND METHOD FOR IMPLEMENTING A BOOLEAN FUNCTION 有权
公开(公告)号：US20180091155A1
公开(公告)日：2018-03-29
申请号：US15701478
申请日：2017-09-12
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H03K19/177 , H03K19/173 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/20
CPC分类号： H03K19/17708 , H03K19/00315 , H03K19/0185 , H03K19/094 , H03K19/1733 , H03K19/17768 , H03K19/20
摘要： According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ⋀ b ) ⋁ ( p 1 ⋀ a ) ⋁ ( p 2 ⋀ b ) ) _ ⋀ ( p 3 ⋁ b ⋁ a ) ) ⋁ ( a ⋀ b ⋀ p 4 ) _ .

6. 发明授权

US09692421B2 Non-volatile latch circuit and logic circuit, and semiconductor device using the same 有权
公开(公告)号：US09692421B2
公开(公告)日：2017-06-27
申请号：US13667292
申请日：2012-11-02
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kiyoshi Kato , Jun Koyama
IPC分类号： H01L25/00 , H03K19/00 , H03K19/173 , G11C14/00 , H01L21/8258 , H01L21/84 , H01L27/06 , H01L27/088 , H01L27/12 , H01L29/786 , H03K3/356 , G11C16/02 , H01L27/1156
CPC分类号： H03K19/1733 , G11C14/0063 , G11C16/02 , H01L21/8258 , H01L21/84 , H01L27/0688 , H01L27/088 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L29/7869 , H03K3/356008 , H03K3/35606
摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

7. 发明授权

US09413355B2 Information processing apparatus and control method therefor 有权
标题翻译：信息处理装置及其控制方法
公开(公告)号：US09413355B2
公开(公告)日：2016-08-09
申请号：US14855925
申请日：2015-09-16
申请人： CANON KABUSHIKI KAISHA
发明人： Yoshikazu Sato , Daisuke Matsunaga
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , G06F3/12 , G06K9/00 , G06K9/20 , H04N5/232 , H04N21/234
CPC分类号： H03K19/1733 , G06F3/1208 , G06F3/126 , G06K9/00261 , G06K9/209 , H03K19/17724 , H03K19/17756 , H03K19/1776 , H04N5/23219 , H04N21/23418
摘要： An information processing apparatus comprises: a programmable processing unit capable of changing a circuit configuration by a configuration; a first control unit connected to the programmable processing unit, that instructs the programmable processing unit to perform a first configuration for a first job to be processed by the first control unit, and processes the first job by means of the programmable processing unit which has changed the circuit configuration according to the instruction; and a second control unit connected to the programmable processing unit, wherein the first control unit further instructs the programmable processing unit to perform a second configuration for a second job to be processed by the second control unit, and wherein the second control unit processes the second job by means of the programmable processing unit which has changed the circuit configuration according to the instruction.
摘要翻译：一种信息处理装置，包括：能够通过配置改变电路配置的可编程处理单元; 连接到可编程处理单元的第一控制单元，其指示可编程处理单元对由第一控制单元处理的第一作业执行第一配置，并且通过已经改变的可编程处理单元处理第一作业电路配置按照说明书; 以及连接到所述可编程处理单元的第二控制单元，其中所述第一控制单元进一步指示所述可编程处理单元对所述第二控制单元要处理的第二作业执行第二配置，并且其中所述第二控制单元处理所述第二控制单元通过可编程处理单元进行工作，该可编程处理单元根据该指令改变了电路配置。

8. 发明授权

US09287878B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09287878B2
公开(公告)日：2016-03-15
申请号：US14689262
申请日：2015-04-17
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Nora Bjorklund , Takeshi Aoki , Yoshiyuki Kurokawa
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/1733 , H03K19/17736
摘要： A dynamic reconfigurable semiconductor device is provided. The semiconductor device includes two logic blocks, a pass transistor, two selection transistors and a precharge transistor. The two selection transistors are arranged to sandwich the pass transistor so that a source and a drain of the pass transistor are located between the sources of the two selection transistors. The sources and the drains of the two selection transistors are located between the two logic blocks. When the two selection transistors are in off-state, a potential can be supplied to the source or the drain of the pass transistor via the precharge transistor, and by electrical conduction, another potential for a context is applied to the gate of the pass transistor. When the context is executed, the gate of the pass transistor is in a floating state, the two selection transistors are in on-state, and the precharge transistor is in off-state.
摘要翻译：提供动态可重构半导体器件。半导体器件包括两个逻辑块，传输晶体管，两个选择晶体管和预充电晶体管。两个选择晶体管被布置成夹持传输晶体管，使得传输晶体管的源极和漏极位于两个选择晶体管的源极之间。两个选择晶体管的源极和漏极位于两个逻辑块之间。当两个选择晶体管处于截止状态时，可以通过预充电晶体管将电位提供给传输晶体管的源极或漏极，并且通过电导通，将上下文的另一个电位施加到传输晶体管的栅极。当执行上下文时，传输晶体管的栅极处于浮置状态，两个选择晶体管处于导通状态，并且预充电晶体管处于截止状态。

9. 发明授权

US08719549B2 Device to reconfigure multi-level logic networks, method to reconfigure multi-level logic networks, device to modify logic networks, and reconfigurable multi-level logic network 失效
标题翻译：重新配置多级逻辑网络的设备，重新配置多级逻辑网络的方法，修改逻辑网络的设备和可重配置的多级逻辑网络
公开(公告)号：US08719549B2
公开(公告)日：2014-05-06
申请号：US12294763
申请日：2007-03-02
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： H03K19/1733
摘要： To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.
摘要翻译：提供一种重新配置多级逻辑网络的设备，其以简单的方式实现具有小电路面积和低功耗的多级逻辑网络的逻辑修改和重新配置。例如，在用于删除对应于输入向量b的对象逻辑函数F（X）的输出向量F（b）的逻辑修改之后重新配置多级逻辑网络的情况下，逐个选择未修改的pq元素从最近的pq元素EG到输出侧。此时，在比选择的pq元素更接近输入侧的pq元件的输出值之中，对应于与输入矢量b以外的任何输入变量X相对应的输出值的输入矢量的输出值被认为是修改的，因此未选中的。然后，将与输入向量b对应的选择的输出值重写为“无效值”。

10. 发明授权

US08674722B2 Semiconductor programmable device 有权
标题翻译：半导体可编程器件
公开(公告)号：US08674722B2
公开(公告)日：2014-03-18
申请号：US13324594
申请日：2011-12-13
申请人： Kazutami Arimoto
发明人： Kazutami Arimoto
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1733
摘要： An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.
摘要翻译： ePLX单元包括具有SRAM和MUX的逻辑单元，以及具有用于在逻辑单元中建立布线连接的SRAM和TG的开关单元。当复合模块被设置为第一模式时，加法/标志控制单元分别使用SRAM作为数据字段和标志字段，以依照下述方式自主地控制每个数据字段和标志字段的读取地址存储在标志字段中的控制标志。此外，当复合模块被设置为第二模式时，加法/标志控制单元将配置信息写入每个SRAM以重新配置逻辑电路。因此，电路配置的粒度可以变化，这允许在配置功能时提高灵活性。

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