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1. 发明申请

US20190236750A1 OPTIMIZING COMPILATION OF SHADERS 审中-公开
公开(公告)号：US20190236750A1
公开(公告)日：2019-08-01
申请号：US16263778
申请日：2019-01-31
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： Ivan NEVRAEV , Cole BROOKING , J. Andrew GOOSSEN , Eric CHRISTOFFERSEN , Jason STRAYER
IPC分类号： G06T1/20 , G09G5/36
CPC分类号： G06T1/20 , G09G5/363 , G09G2360/02 , G09G2360/10
摘要： To optimize the compilation of shaders for execution within an application, a computer system discovers the context in which the shaders are executed. The application is compiled and executed on a target platform. Snapshots of the application during execution are captured. A snapshot includes data and commands passed between the central processing unit and the graphics processing unit of the target platform to generate a single frame of graphics data. The shaders used in these snapshots are identified. These shaders are compiled with a number of different permutations of available compiler options, resulting in sets of differently compiled shaders. The snapshot is re-executed with the sets of differently compiled shaders, and performance is measured. The set of compiler options that results in compiled shaders providing better performance can be used as the set of compilation parameters for the set of shaders for this application.

2. 发明申请

US20170345401A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM SELECTIVELY OPERATING AS ONE OF A BIG ENDIAN OR LITTLE ENDIAN SYSTEM 审中-公开
公开(公告)号：US20170345401A1
公开(公告)日：2017-11-30
申请号：US15678012
申请日：2017-08-15
申请人： Renesas Electronics Corporation
发明人： Goro SAKAMAKI , Yuri AZUMA
IPC分类号： G09G5/39 , G06F9/48 , G06F13/10 , G06F13/20 , G09G3/20 , G06F13/42 , G06F7/76 , G06F13/40 , G09G3/36
CPC分类号： G09G5/39 , G06F7/768 , G06F9/4806 , G06F13/10 , G06F13/102 , G06F13/20 , G06F13/4013 , G06F13/4022 , G06F13/4063 , G06F13/4221 , G09G3/2096 , G09G3/36 , G09G3/3648 , G09G3/3674 , G09G2310/08 , G09G2360/10
摘要： The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

3. 发明申请

US20170329395A1 DATE PROCESSING SYSTEMS 审中-公开
公开(公告)号：US20170329395A1
公开(公告)日：2017-11-16
申请号：US15590300
申请日：2017-05-09
申请人： ARM Limited
发明人： Lars Oskar Flordal
IPC分类号： G06F3/01 , G06T15/04 , G06T15/00 , G06T11/00 , G06T1/60 , G09G5/36 , H04N19/20
CPC分类号： G06F3/011 , G06F3/14 , G06T1/60 , G06T11/001 , G06T15/005 , G06T15/04 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/08 , G09G2360/10 , H04N19/20 , H04N19/42
摘要： In a data processing system that includes a graphics processor and a video processor, graphics textures for use by the graphics processor are stored as encoded frames of video data. The video processor then decodes the video frames to reproduce the graphics texture(s) that the video frames encode, and stores the decoded graphics texture or textures in memory for use by the graphics processor.The graphics processor then reads the decoded graphics textures for use when generating its render outputs, such as output frames for display.

4. 发明申请

US20170272686A1 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD 有权
公开(公告)号：US20170272686A1
公开(公告)日：2017-09-21
申请号：US15453924
申请日：2017-03-09
申请人： CANON KABUSHIKI KAISHA
发明人： Takehito Fukushima , Ikuo Takanashi
IPC分类号： H04N5/57 , H04N5/445
CPC分类号： H04N5/57 , G09G5/10 , G09G2320/0271 , G09G2360/10 , G09G2360/16 , G09G2370/04 , H04N5/44504
摘要： An information processing apparatus includes: an acquisition unit configured to acquire input brightness information; a generation unit configured to generate display image data by converting gradation characteristics of input image data based on display characteristics; and a notification unit configured to perform, based on the display characteristics and the input brightness information, at least one of first notification processing to provide notification of information indicating that a display unit is able to display the display image data with brightness of the input image data, and second notification processing to provide notification of information indicating that the display unit is not able to display the display image data with the brightness.

5. 发明申请

US20170249920A1 VARIABLE REFRESH RATE VIDEO CAPTURE AND PLAYBACK 有权
公开(公告)号：US20170249920A1
公开(公告)日：2017-08-31
申请号：US15054019
申请日：2016-02-25
申请人： NVIDIA Corporation
发明人： David COOK , Lu LIU
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G5/363 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2360/10 , G09G2360/18 , G09G2370/022 , G09G2370/16
摘要： A method for displaying video. The method includes executing an application at a processor. As instructed by the processor when executing the application, the method includes rendering a plurality of image frames at a plurality of graphics processing units (GPUs). The method includes determining information related to relative timing between renderings of the plurality of image frames. The method includes encoding the plurality of image frames into a video file. The method includes encoding the information into the video file.

6. 发明申请

US20170208219A1 DISPLAY CONTROLLER FOR GENERATING VIDEO SYNC SIGNAL USING EXTERNAL CLOCK, AN APPLICATION PROCESSOR INCLUDING THE CONTROLLER, AND AN ELECTRONIC SYSTEM INCLUDING THE CONTROLLER 审中-公开
公开(公告)号：US20170208219A1
公开(公告)日：2017-07-20
申请号：US15405640
申请日：2017-01-13
申请人： Samsung Electronics Co., Ltd.
发明人： Jong Hyup Lee , Min Chul Kim , Sung Hoo Choi
IPC分类号： H04N5/06 , G09G3/20
CPC分类号： H04N5/06 , G09G3/2096 , G09G5/008 , G09G5/12 , G09G2310/08 , G09G2320/0247 , G09G2360/10 , G09G2370/10
摘要： In a display controller for generating a video sync signal using an external clock, he display controller includes an initializer configured to initialize an internal parameter in response to a frame start signal. A sync signal generation circuit is configured to count the external clock, increase the internal parameter, and generate the video sync signal according to a result of comparing the internal parameter that has been increased with a setting value. An original use of the external clock may not be generating the video sync signal.

7. 发明申请

US20160364011A1 HUMAN MACHINE INTERFACE CONTROLLER 审中-公开
标题翻译：人机界面控制器
公开(公告)号：US20160364011A1
公开(公告)日：2016-12-15
申请号：US14739624
申请日：2015-06-15
申请人： Microsoft Technology Licensing, LLC.
发明人： David Bohn
IPC分类号： G06F3/033 , A63F13/825 , G09G3/00 , A63F13/23 , H04M1/725 , H04N9/31
CPC分类号： G06F3/033 , A63F13/23 , A63F13/825 , G06F1/1632 , G06F1/1639 , G06F1/1686 , G06F3/017 , G06F3/0304 , G06F3/0317 , G06F3/0346 , G06F3/04815 , G06F3/0485 , G09G3/002 , G09G2320/06 , G09G2360/10 , H04M1/72544 , H04N9/3141
摘要： A handheld controller for controlling a computer video game that receives streaming video data defining images of regions of a virtual game environment that the computer transmits; projects the images defined by the video data along a projection axis to form the images on a surface that the projection axis intersects so that a user may view and interact with the images; transmits position and/or orientation (P/O) data that defines positions and/or orientations of the projection axis to control for which regions of the virtual environment the computer streams video; and comprises an actuator operable to disengage the P/O data so that video data received from the computer does not change responsive to changes in position and/or orientation of the controller.
摘要翻译：一种用于控制计算机视频游戏的手持式控制器，其接收定义所述计算机发送的虚拟游戏环境区域的图像的流视频数据; 沿着投影轴投影由视频数据定义的图像，以在投影轴相交的表面上形成图像，使得用户可以观看图像并与图像进行交互; 传输定义投影轴的位置和/或取向的位置和/或取向（P / O）数据，以控制计算机流视频的虚拟环境的哪些区域; 并且包括致动器，其可操作以使P / O数据脱离，使得从计算机接收的视频数据不响应于控制器的位置和/或取向的改变而改变。

8. 发明申请

US20160274364A1 MICRODISPLAY BASED IMMERSIVE HEADSET 有权
公开(公告)号：US20160274364A1
公开(公告)日：2016-09-22
申请号：US15149735
申请日：2016-05-09
申请人： eMagin Corporation
发明人： Jerome T. Carollo , Amal Ghosh , John Chi-Liang Ho , Andrew Thomas Manning Rosen
IPC分类号： G02B27/01 , G09G5/00
CPC分类号： G02B27/0176 , G02B27/0172 , G02B27/0179 , G02B2027/0132 , G02B2027/0152 , G02B2027/0154 , G02B2027/0156 , G02B2027/0161 , G02B2027/0169 , G02B2027/0178 , G02B2027/0181 , G06T19/006 , G09G5/005 , G09G2360/10 , H04N13/286
摘要： An immersive headset device is provided that includes a display portion and a body portion. The display portion may include microdisplays having a compact size. The microdisplays may be movable (e.g., rotational) relative to the body portion and can be moved (e.g., rotated) between a flipped-up position and a flipped-down position. In some instances, when the microdisplays are flipped up, the headset provides an augmented reality (AR) mode to a user, and when the microdisplays are flipped down, the headset provide a virtual reality (VR) mode to the user. In certain implementations, the headset includes an electronics source module to provide power and/or signal to the microdisplays. The electronics source module can be attached to a rear of the body portion in order to provide advantageous weight distribution about the head of the user.

9. 发明申请

US20160225309A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20160225309A1
公开(公告)日：2016-08-04
申请号：US15095051
申请日：2016-04-09
申请人： Renesas Electronics Corporation
发明人： Goro SAKAMAKI , Yuri AZUMA
IPC分类号： G09G3/20 , G06F13/10 , G09G3/36 , G06F13/40
CPC分类号： G09G5/39 , G06F7/768 , G06F9/4806 , G06F13/10 , G06F13/102 , G06F13/20 , G06F13/4013 , G06F13/4022 , G06F13/4063 , G06F13/4221 , G09G3/2096 , G09G3/36 , G09G3/3648 , G09G3/3674 , G09G2310/08 , G09G2360/10
摘要： The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.
摘要翻译：本发明是提供一种半导体装置，即使在外部不识别到并行接口的端面，也能够正确地切换外部的端子。半导体器件包括开关电路和第一寄存器。开关电路是否将与外部的并行接口用作大端或小端。第一寄存器保存开关电路的控制数据。当第一预定控制信息（即使其高位和低位比特位置被转置时在特定比特位置的值不变）的第一预定控制信息被提供给第一寄存器时，切换电路将并行接口视为小端，并且将并行接口视为大端，即使第二预定控制信息（即使其高位和低位比特位置被转置也在特定比特位置的值不变）被提供给第一寄存器。无论端点设置状态如何，控制信息都可以正确输入，而不受端序设置状态的影响。

10. 发明授权

US09336048B2 Semiconductor device and data processing system selectively operating as one of a big endian or little endian system 有权
公开(公告)号：US09336048B2
公开(公告)日：2016-05-10
申请号：US14802836
申请日：2015-07-17
申请人： Renesas Electronics Corporation
发明人： Goro Sakamaki , Yuri Azuma
IPC分类号： G06F9/30 , G06F13/10 , G06F9/48 , G06F13/40 , G06F7/76 , G06F13/20 , G06F13/42
CPC分类号： G09G5/39 , G06F7/768 , G06F9/4806 , G06F13/10 , G06F13/102 , G06F13/20 , G06F13/4013 , G06F13/4022 , G06F13/4063 , G06F13/4221 , G09G3/2096 , G09G3/36 , G09G3/3648 , G09G3/3674 , G09G2310/08 , G09G2360/10
摘要： The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

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