专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140201585A1 State-Split Based Endec 有权
标题翻译：基于状态分割的Endec
公开(公告)号：US20140201585A1
公开(公告)日：2014-07-17
申请号：US13742340
申请日：2013-01-15
申请人： LSI Corporation
发明人： Razmik Karabed , Shaohua Yang , Wu Chang , Victor Krachkovsky
IPC分类号： G06F11/14
CPC分类号： G06F11/14 , G11B20/1833 , G11C11/26 , G11C11/5628 , G11C11/5642 , H03M5/145
摘要： Various embodiments of the present invention provide systems and methods for encoding and decoding data for constrained systems with state-split based encoders and decoders.
摘要翻译：本发明的各种实施例提供了用于基于状态分割的编码器和解码器的受限制系统的数据的编码和解码的系统和方法。

2. 发明申请

US20120033499A1 FLASH MEMORY DEVICE AND READING METHOD THEREOF 有权
标题翻译：闪存存储器件及其读取方法
公开(公告)号：US20120033499A1
公开(公告)日：2012-02-09
申请号：US13198126
申请日：2011-08-04
申请人： Boh-Chang KIM
发明人： Boh-Chang KIM
IPC分类号： G11C16/26
CPC分类号： G11C16/04 , G11C11/26 , G11C11/5628 , G11C16/0483
摘要： A flash memory device and reading method of the flash memory device. The reading method includes determining a read voltage set of memory cells corresponding to a first word line from at least one of flag cell data of the first word line and flag cell data of a second word line adjacent to the first word line, and reading the memory cells corresponding to the first word line according to the determined read voltage set.
摘要翻译：一种闪速存储装置和闪存装置的读取方法。读取方法包括从第一字线的标志单元数据和与第一字线相邻的第二字线的标志单元数据中的至少一个确定与第一字线相对应的存储单元的读取电压组，并读取根据确定的读取电压设置对应于第一字线的存储单元。

3. 发明申请

US20110280084A1 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
标题翻译：在存储器件和系统中确定和使用软数据
公开(公告)号：US20110280084A1
公开(公告)日：2011-11-17
申请号：US12778577
申请日：2010-05-12
申请人： William H. Radke , Zhenlei Shen , Peter Feeley
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

4. 发明申请

US20150255163A1 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
标题翻译：在存储器件和系统中确定和使用软数据
公开(公告)号：US20150255163A1
公开(公告)日：2015-09-10
申请号：US14719519
申请日：2015-05-22
申请人： Micron Technology, Inc.
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

5. 发明申请

US20140233322A1 ADAPTIVE ARCHITECTURE IN A CHANNEL DETECTOR FOR NAND FLASH CHANNELS 有权
标题翻译：用于NAND FLASH通道的通道检测器中的自适应架构
公开(公告)号：US20140233322A1
公开(公告)日：2014-08-21
申请号：US13775559
申请日：2013-02-25
申请人： LSI CORPORATION
发明人： Yunxiang Wu , Jamal Riani
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C11/26 , G11C11/5642 , G11C16/3404
摘要： An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value.
摘要翻译：一种包括被配置为存储数据的存储器和控制器的装置。控制器可以被配置为处理多个输入/输出请求以从/从存储器读/写。控制器被配置为（i）基于估计设置阈值电压的值，（ii）确定读取是否成功，（iii）如果读取不成功，则执行具有变化值的多个读取阈值电压，（iv）基于多个读取从查找表读取校准值，并且（v）响应于校准值设置阈值。

6. 发明授权

US4719457A Information input/output display device 失效
标题翻译：信息输入/输出显示装置
公开(公告)号：US4719457A
公开(公告)日：1988-01-12
申请号：US702225
申请日：1985-02-15
申请人： Masaaki Kitajima , Masahiro Takasaka , Yoshiharu Nagae
发明人： Masaaki Kitajima , Masahiro Takasaka , Yoshiharu Nagae
IPC分类号： G06F3/044 , G09F9/35 , G09G3/18 , G09G3/36 , G11C11/22 , G11C11/26 , G11C11/56
CPC分类号： G11C11/26 , G09G3/3629 , G11C11/22 , G09G2320/041
摘要： An information input/output display device comprising a dielectric which is held in a portion between one electrode and the other electrode opposite to each other and which has at least a first state and a second state of unequal capacitances, means to change the capacitance of the dielectric, capacitance holding means to hold at least temporarily a value of the capacitance of the dielectric in the first state, and means to compare the value of the capacitance of the dielectric with the value of the capacitance held by the capacitance holding means, whereby information can be read out without being affected by fluctuations in a distance d between the electrodes or/and in an ambient temperature T.
摘要翻译：一种信息输入/输出显示装置，包括保持在一个电极和另一个电极彼此相对的部分中并且具有至少第一状态和第二不等电容状态的电介质的电介质，电介质，电容保持装置，用于至少暂时保持第一状态下的电介质的电容值，以及将电介质的电容值与由电容保持装置保持的电容的值进行比较的装置，由此信息可以在不受电极之间的距离d的波动或/和环境温度T的影响的情况下读出。

7. 发明授权

US4200822A MOS Circuit for generating a square wave form 失效
标题翻译：用于产生方波形的MOS电路
公开(公告)号：US4200822A
公开(公告)日：1980-04-29
申请号：US905620
申请日：1978-05-15
申请人： John W. V. Miller
发明人： John W. V. Miller
IPC分类号： G09G3/28 , G09G3/288 , G11C11/26 , H03K21/18 , H05B39/00 , H05B41/00
CPC分类号： G09G3/294 , G09G3/296 , G09G3/297 , G11C11/26 , H03K21/18
摘要： A circuit for generating a square wave form which circuit comprises two MOSFETs and is driven by only one control logic signal. A first MOSFET is connected between a ground potential power supply and the circuit output line while a second MOSFET is connected between the circuit output line and a positive potential power supply. The gate of the second MOSFET is connected to the source of the first MOSFET which has a gate connected to receive the control logic signal. When the logic signal is at a high level, the first MOSFET is turned on and the gate of the second MOSFET is pulled down to ground potential such that the second MOSFET is turned off. Thus, the circuit output line will be near the ground potential. When the logic signal switches to a low level, the first MOSFET is turned off and the voltage across a capacitor which has been charged by a power supply causes the second MOSFET to turn on such that the circuit output line will be near the positive potential. This circuit is typically used to drive capacitive type loads such as those found in gas discharge display devices.
摘要翻译：用于产生方波形的电路，该电路包括两个MOSFET，并且仅由一个控制逻辑信号驱动。第一个MOSFET连接在地电位电源和电路输出线之间，而第二个MOSFET连接在电路输出线和正电位电源之间。第二MOSFET的栅极连接到具有连接到栅极的第一MOSFET的源极以接收控制逻辑信号。当逻辑信号处于高电平时，第一个MOSFET导通，第二个MOSFET的栅极被下拉到地电位，使得第二个MOSFET关断。因此，电路输出线将接近地电位。当逻辑信号切换到低电平时，第一个MOSFET关断，并且由电源充电的电容器两端的电压导致第二个MOSFET导通，使得电路输出线将接近正电位。该电路通常用于驱动诸如在气体放电显示装置中发现的电容型负载。

8. 发明授权

US09293214B2 Determining and using soft data in memory devices and systems 有权
公开(公告)号：US09293214B2
公开(公告)日：2016-03-22
申请号：US14719519
申请日：2015-05-22
申请人： Micron Technology, Inc.
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C11/34 , G11C16/26 , G11C11/26 , G11C11/56 , G11C7/14 , G11C16/34 , G11C29/02 , G11C29/42 , G11C29/50
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

9. 发明授权

US08854889B2 Flash memory device and reading method thereof 有权
标题翻译：闪存装置及其读取方法
公开(公告)号：US08854889B2
公开(公告)日：2014-10-07
申请号：US13954428
申请日：2013-07-30
申请人： Samsung Electronics Co., Ltd.
发明人： Boh-chang Kim
IPC分类号： G11C11/34 , G11C16/04 , G11C11/26 , G11C11/56
CPC分类号： G11C16/04 , G11C11/26 , G11C11/5628 , G11C16/0483
摘要： A flash memory device and reading method of the flash memory device. The reading method includes determining a read voltage set of memory cells corresponding to a first word line from at least one of flag cell data of the first word line and flag cell data of a second word line adjacent to the first word line, and reading the memory cells corresponding to the first word line according to the determined read voltage set.
摘要翻译：一种闪速存储装置和闪存装置的读取方法。读取方法包括从第一字线的标志单元数据和与第一字线相邻的第二字线的标志单元数据中的至少一个确定与第一字线相对应的存储单元的读取电压组，并读取根据确定的读取电压设置对应于第一字线的存储单元。

10. 发明申请

US20130286736A1 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
公开(公告)号：US20130286736A1
公开(公告)日：2013-10-31
申请号：US13903250
申请日：2013-05-28
申请人： Micron Technology, Inc.
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式