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1. 发明授权

US09716394B1 Lighting control device with removable power supply charge state indication and a method therefor 有权
公开(公告)号：US09716394B1
公开(公告)日：2017-07-25
申请号：US15207651
申请日：2016-07-12
申请人： ABL IP Holding LLC
发明人： Matthew A. Clement
IPC分类号： H02J7/00 , G01R31/36 , G06F1/32 , H05B37/02 , H03K21/18
CPC分类号： G06F1/3212 , G01R31/362 , G01R31/3624 , G01R31/3637 , G01R31/3686 , G01R31/3689 , H03K21/18 , H05B37/0272 , Y02D10/174
摘要： Examples of methods and devices provide a charge level indication of a removable power source of a lighting control device. An example method may include receiving an input indication. A duration of the input is measured. If the measured duration exceeds a predetermined input duration threshold, an indication of a charge level of a removable power supply is obtained. The obtained charge level indication is compared, by a control unit, to a threshold charge level of the power supply. The threshold charge level is indicates an amount of charge remaining in the power supply. In response to a comparison result, an indicator light signal is applied to an indicator light. An example device may include a removable electrical power supply, an input device, an indicator light, and a control unit all of which may cooperate to perform a disclosed method.

2. 发明授权

US07250796B2 Semiconductor device including an output circuit having a reduced output noise 失效
标题翻译：半导体装置包括具有降低的输出噪声的输出电路
公开(公告)号：US07250796B2
公开(公告)日：2007-07-31
申请号：US11223937
申请日：2005-09-13
申请人： Hideto Hidaka , Masakazu Hirose
发明人： Hideto Hidaka , Masakazu Hirose
IPC分类号： H03K21/18
CPC分类号： H03K19/00361
摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.
摘要翻译：当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。当驱动晶体管导通时，输出节点以高速放电到地电位。当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。提供了可以有效地防止产生振铃而不增加访问时间的输出电路。提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。高速提供稳定的输出信号。

3. 发明授权

US4692933A Electro-mechanical integrator 失效
标题翻译：机电一体机
公开(公告)号：US4692933A
公开(公告)日：1987-09-08
申请号：US843369
申请日：1986-03-24
申请人： David J. Wroblewski , John W. Robertson, Jr.
发明人： David J. Wroblewski , John W. Robertson, Jr.
IPC分类号： G06F7/64 , G01F15/075 , G01R19/252 , G06F7/62 , G06F7/68 , H03K21/02 , G01R23/10 , H03K21/18
CPC分类号： G01F15/0755 , G01R19/252 , G06F7/62 , G06F7/68
摘要： An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.
摘要翻译：用于集成线性电压信号的电子积分器利用电压 - 频率转换器将电压转换为输入频率。二进制计数器计数输入频率的脉冲。二进制计数器产生施加到缩放电路的第一工作频率和比工作频率高得多的另一校准频率。但是，两者都与输入频率成比例。缩放电路将工作频率缩放到选定的范围以形成计数信号。使用双极开关，将校准频率或计数频率应用于脉冲计数器，脉冲计数器用于通过对标定计数信号的脉冲进行计数来积分输入电压信号，或者可以使用校准频率校准积分器它可以快速增加脉冲计数器。

4. 发明授权

US4689575A Clock synchronization circuit for a computer timer 失效
标题翻译：电脑定时器的时钟同步电路
公开(公告)号：US4689575A
公开(公告)日：1987-08-25
申请号：US755012
申请日：1985-07-15
申请人： Russell G. Ott
发明人： Russell G. Ott
IPC分类号： H03K5/00 , G04G7/00 , G06F1/14 , G06F15/78 , H03K21/18 , H03K1/17 , H03K7/00 , H03K17/00
CPC分类号： G04G7/00 , H03K21/18
摘要： A timing system which includes a timer circuit, a source of first clock pulses for advancing the timer circuit, and a circuit for reading out the timer circuit in synchronism advanced therewith and where there is also included a second source of clock pulses asynchronous with respect to the first source of clock pulses, a synchronizing circuit is provided for storing an indication of the receipt of each second clock source pulse. Then the timer is advanced only when a pulse is produced by the first clock source and the indication is present that a signal has been produced by the second clock source.
摘要翻译：一种定时系统，包括定时器电路，用于使定时器电路前进的第一时钟脉冲的源，以及用于与其同步地读出定时器电路的电路，并且其中还包括第二时钟脉冲源相对于第一时钟脉冲源，提供用于存储每个第二时钟源脉冲的接收指示的同步电路。然后，只有当第一时钟源产生脉冲并且存在由第二时钟源产生信号的指示时，定时器才进行。

5. 发明授权

US4309598A Variable rate data entry apparatus and method 失效
标题翻译：可变速率数据输入装置及方法
公开(公告)号：US4309598A
公开(公告)日：1982-01-05
申请号：US79632
申请日：1979-09-27
申请人： James M. Davis, Jr.
发明人： James M. Davis, Jr.
IPC分类号： H03K21/18 , H03K23/66 , H03K21/36 , G06M3/14
CPC分类号： H03K23/66 , H03K21/18
摘要： A digital display updated by inputs from a manual control having a plurality of tactile detents. A counter is loaded with a predetermined number and then decremented at a fixed rate until the number reaches one. The fixed rate is either the program cycle time of a microprocessor embodiment or the clock time of a circuit embodiment. Whenever a detent of the control is detected, the then current value of the counter is added to or subtracted from the display and the counter is again loaded with the predetermined number.
摘要翻译：由具有多个触觉制动器的手动控制器的输入更新的数字显示器。计数器加载预定数量，然后以固定速率递减，直到数量达到一个。固定速率是微处理器实施例的编程周期时间或电路实施例的时钟时间。每当检测到控制的定位时，计数器的当前值被添加到显示器上或从显示器中减去，并且计数器再次以预定数量加载。

6. 发明授权

US4249070A Counter/timer with incremental indicators 失效
标题翻译：带增量指示器的计数器/计时器
公开(公告)号：US4249070A
公开(公告)日：1981-02-03
申请号：US947200
申请日：1978-09-29
申请人： David D. Miller
发明人： David D. Miller
IPC分类号： G04F1/00 , H03K21/18 , G06M3/02
CPC分类号： G04F1/005 , H03K21/18
摘要： In a timer or counter for timing to a selected time or counting to a selected count, there is included digital counting means and means for creating an output signal when the counting means counts to a selected number. In this type of device, there is further provided a plurality of two state indicator elements and means responsive to the counting means for changing the state of one of the elements after the timer or counter has progressed through each of several, preselected portions of the selected number being counted.
摘要翻译：在定时器或计数器中，用于定时到所选择的时间或计数到所选择的计数，包括数字计数装置和用于当计数装置计数到选定数量时产生输出信号的装置。在这种类型的设备中，还提供了多个两个状态指示器元件和装置，其响应于计数装置，用于在定时器或计数器已经进行到所选择的几个预选部分中的每一个之后改变其中一个元件的状态正在计数。

7. 发明授权

US4237373A Magnetic tape running state and tape run amount display device 失效
标题翻译：磁带运行状态和磁带运行量显示装置
公开(公告)号：US4237373A
公开(公告)日：1980-12-02
申请号：US937899
申请日：1978-08-29
申请人： Masanao Okatani , Hiroshi Onishi , Yoshiaki Ishibashi , Reisuke Sato , Hisashi Suganuma , Tomohisa Yokogawa , Yoshiharu Ueki , Haruo Kama , Tadashi Kosuga , Tadashi Ogawa
发明人： Masanao Okatani , Hiroshi Onishi , Yoshiaki Ishibashi , Reisuke Sato , Hisashi Suganuma , Tomohisa Yokogawa , Yoshiharu Ueki , Haruo Kama , Tadashi Kosuga , Tadashi Ogawa
IPC分类号： G11B15/093 , G11B27/13 , G11B27/34 , H03J1/04 , H03K21/18 , G06M3/06
CPC分类号： G11B15/093 , G11B27/13 , G11B27/34 , H03J1/04 , H03K21/18
摘要： The present invention is a magnetic tape running state and tape run amount display device which displays visually the running direction and speed or the run amount and direction of the magnetic tape. An up-down counter is provided with a clock input signal having a pulse generated in correspondence with the run of the tape and is also provided with a count control signal. The count control signal has an UP signal generated when the tape is being transported in a first or forward direction, and has a DOWN signal generated when the tape is being transported in a second or reverse direction. The up-down counter provides a binary output count signal to a display circuit in correspondence with the clock input signal and the count control signal. The up-down counter can also be provided with a reset input responsive to a reset signal which acts to reset the count back to logic 0. The display circuit provides a visual representation of the binary output signal, and may include a first binary-to-digital decoder and a second binary-to-digital decoder, each being responsive to a preselected portion of the binary bits provided by the up-down counter. A plurality of light emitting diodes are connected between decimal output lines of the first and second binary-to-digital decoders for providing a visual indication of the tape running state and run amount. In one arrangement, the diodes are arranged to define a line. The display circuit also can be responsive to the binary tuning signal provided by an electronic tuning type receiver.
摘要翻译：本发明是一种磁带运行状态和磁带运行量显示装置，其可视地显示磁带的运行方向和速度或运行量和运行方向。上下计数器具有时钟输入信号，该时钟输入信号具有与磁带的行程相对应生成的脉冲，并且还具有计数控制信号。计数控制信号具有在磁带沿第一或前进方向传输时产生的UP信号，并且当磁带沿第二或相反方向传输时产生一个DOWN信号。升降计数器根据时钟输入信号和计数控制信号向显示电路提供二进制输出计数信号。升降计数器还可以具有响应于复位信号的复位输入，该复位信号用于将计数重置为逻辑0.该显示电路提供二进制输出信号的可视表示，并且可以包括第一二进制数字解码器和第二二进制数字解码器，每个解码器响应于由递减计数器提供的二进制位的预选部分。多个发光二极管连接在第一和第二二进制数字解码器的十进制输出线之间，用于提供磁带运行状态和运行量的可视指示。在一种布置中，二极管被布置成限定线。显示电路还可以响应由电子调谐型接收器提供的二进制调谐信号。

8. 发明授权

US3962701A Coded counting sequence and logic implementation thereof to drive a display pattern 失效
标题翻译：编码计数序列及其逻辑实现来驱动显示模式
公开(公告)号：US3962701A
公开(公告)日：1976-06-08
申请号：US535642
申请日：1974-12-23
申请人： Gary L. Heimbigner
发明人： Gary L. Heimbigner
IPC分类号： H03K21/00 , H03K21/08 , G06K15/18 , H03K21/18
CPC分类号： H03K21/08 , H03K21/00
摘要： An integrated circuit is disclosed providing the logic to generate a unique binary coded numerical counting sequence and a corresponding decoded segment select sequence to subsequently activate particular segments comprising a display pattern at predetermined times. A minimum number of logic input terms and respective logic gates are required to implement the instant sequence to thereby reduce the space consumed by the circuit and the cost thereof.
摘要翻译：公开了集成电路，其提供用于生成唯一的二进制编码数字计数序列和对应的解码段选择序列的逻辑，以随后在预定时间激活包括显示图案的特定段。需要最少数量的逻辑输入项和相应的逻辑门来实施本次序列，从而减少电路消耗的空间及其成本。

9. 发明授权

US3805255A Scanning light emitting diode display of digital information 失效
标题翻译：扫描二极管显示数字信息
公开(公告)号：US3805255A
公开(公告)日：1974-04-16
申请号：US29090672
申请日：1972-09-21
申请人： HEWLETT PACKARD CO
发明人： BAKER C
IPC分类号： G06F11/32 , G06F3/147 , G09G3/14 , G08B5/36 , H03K21/18
CPC分类号： G09G3/14
摘要： A digital logic display in which a row of light emitting diodes (LED''s) is used to indicate the logic state of each bit of a sequence of bits present at one input. Another row of light emitting diodes is used in one mode to indicate the logic state of each bit of a sequence of bits present at another input, and in another mode to indicate the logic state of each bit of a sequence of bits that result from performing a pre-selected Boolean operation on corresponding bits of the two input sequences. By means of associated digital circuitry, the original input bit sequences are broken up into shorter sequences which are cycled in closed loops in a series of shift registers, thereby preserving the original data intact while sampled bits are subjected to preselected Boolean operations. Also this procedure facilitates the use of a scanning mechanism whereby each output LED is responsive to the logic state of selected bits only periodically.
摘要翻译：一种数字逻辑显示器，其中一行发光二极管（LED）用于指示存在于一个输入端的位序列的每个位的逻辑状态。在一种模式中使用另一行发光二极管来指示存在于另一输入端的位序列的每个位的逻辑状态，而在另一模式中指示由执行中产生的位序列的每个位的逻辑状态对两个输入序列的相应位进行预先选择的布尔运算。通过相关联的数字电路，原始输入位序列被分解成在一系列移位寄存器的循环中循环的较短序列，从而在采样位经受预选布尔运算时保持原始数据完整。此外，该程序有助于使用扫描机构，由此每个输出LED仅周期性地响应所选位的逻辑状态。

10. 发明授权

US3805029A Digital counter 失效
标题翻译：数字计数器
公开(公告)号：US3805029A
公开(公告)日：1974-04-16
申请号：US23732372
申请日：1972-03-23
申请人： BORISOV K , KUZEMKO V , UTYAKOV L , TOKOVENKO S , SITNIKOV L
发明人： KUZEMKO V , SITNIKOV L , TOKOVENKO S , UTYAKOV L , BORISOV K
IPC分类号： H03K21/08 , H03K21/18
CPC分类号： H03K21/08
摘要： A digital counter providing indication of the results of the counting, including a multicolumn counter with indicators having like digital electrodes which are combined and controlled by a reference pulse generator with ten outputs, such as with a decimal counter. Each decimal column of the displayed counter includes its own converter for a binary decimal code into a pulse position code whose output is connected through an amplifier to a common electrode, such as the anode of the digital indicator. Counting indication is obtained on the parallel principle simultaneously in all the columns, the indicators being actuated when the pulses on the digital and common electrodes coincide.
摘要翻译：一个提供计数结果指示的数字计数器，包括一个具有类似数字电极的指示器的多列计数器，它们由具有十个输出的参考脉冲发生器组合和控制，如十进制计数器。显示的计数器的每个十进制列包括其自身的二进制十进制代码转换为脉冲位置代码，其输出通过放大器连接到诸如数字指示器的阳极的公共电极。在所有列中同时获得计数指示，当数字和公共电极上的脉冲重合时，指示器被激活。

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