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1. 发明申请

US20190122739A1 RESPONDING TO POWER LOSS 审中-公开
公开(公告)号：US20190122739A1
公开(公告)日：2019-04-25
申请号：US16222160
申请日：2018-12-17
申请人： MICRON TECHNOLOGY, INC.
发明人： Rainer Bonitz
IPC分类号： G11C16/34 , G11C16/08
CPC分类号： G11C16/3418 , G11C14/0063 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/225 , G11C16/26 , G11C16/30
摘要： Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

2. 发明申请

US20180336948A1 MULTI-BLOCK NON-VOLATILE MEMORIES WITH SINGLE UNIFIED INTERFACE 审中-公开
公开(公告)号：US20180336948A1
公开(公告)日：2018-11-22
申请号：US15981920
申请日：2018-05-17
申请人： Aspiring Sky Co. Limited
发明人： Zhijiong LUO , Shu WANG , Xiaoming JIN
IPC分类号： G11C14/00 , G11C16/26 , G11C16/04 , G11C16/10
CPC分类号： G11C14/0063 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C11/005 , G11C16/04 , G11C16/10 , G11C16/107 , G11C16/20 , G11C16/26 , G11C16/32
摘要： A memory system may include one or more hybrid fast memory blocks with m-bit fast volatile random access memory (RAM) cells and N×m bit non-volatile memory (NVM) cells. The memory system may also include one or more other memory blocks with NVM cells. The fast flash memory may buffer the NVM data improving access speed. The different memory blocks may utilize a single, unified interface to communicate with other devices/circuits. The unified interface may be a parallel interface (e.g., flash memory/SRAM combinations), or the unified interface may be a pipeline interface (e.g., system on a chip “SOC” implementations) supporting fast memory read/write operations.

3. 发明申请

US20180166139A1 METHOD AND APPARATUS FOR PROVIDING MULTI-PAGE READ AND WRITE USING SRAM AND NONVOLATILE MEMORY DEVICES 审中-公开
公开(公告)号：US20180166139A1
公开(公告)日：2018-06-14
申请号：US15891284
申请日：2018-02-07
申请人： NEO Semiconductor, Inc.
发明人： Fu-Chang Hsu
IPC分类号： G11C14/00 , G11C11/00 , G11C11/419 , G11C16/10 , G11C16/04
CPC分类号： G11C14/0063 , G11C11/005 , G11C11/419 , G11C16/0483 , G11C16/10
摘要： A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

4. 发明申请

US20180081802A1 HYBRID NON-VOLATILE MEMORY STRUCTURES AND METHODS THEREOF 审中-公开
公开(公告)号：US20180081802A1
公开(公告)日：2018-03-22
申请号：US15704011
申请日：2017-09-14
申请人： Aspiring Sky Co. Limited
发明人： Zhijiong LUO , Shu WANG , Xiaoming JIN
IPC分类号： G06F12/06 , G06F12/02 , G06F13/16
CPC分类号： G11C11/4085 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/1016 , G06F2212/1028 , G06F2212/205 , G06F2212/7203 , G11C5/025 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/10 , G11C11/418 , G11C11/419 , G11C14/00 , G11C14/0063 , G11C16/08 , Y02D10/13 , Y02D10/14
摘要： Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.

5. 发明授权

US09728248B2 Semiconductor structure and memory device including the structure 有权
公开(公告)号：US09728248B2
公开(公告)日：2017-08-08
申请号：US14657914
申请日：2015-03-13
申请人： STMicroelectronics (Rousset) SAS
发明人： François Tailliet , Marc Battista
IPC分类号： G11C11/41 , G11C11/412 , G11C14/00 , G11C16/04 , H01L27/11
CPC分类号： G11C11/41 , G11C11/4125 , G11C14/0054 , G11C14/0063 , G11C16/0416 , H01L23/5226 , H01L27/1104 , H01L29/0847 , H01L29/42364 , H01L29/513 , H01L29/518 , H01L29/788
摘要： A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

6. 发明授权

US09653164B2 Method for integrating non-volatile memory cells with static random access memory cells and logic transistors 有权
公开(公告)号：US09653164B2
公开(公告)日：2017-05-16
申请号：US14656832
申请日：2015-03-13
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Cheong Min Hong , Laureen H. Parker
IPC分类号： G11C14/00 , H01L29/51 , H01L21/265 , H01L21/28 , H01L29/423 , H01L27/11524 , H01L27/11534
CPC分类号： G11C14/0063 , H01L21/26513 , H01L21/28273 , H01L21/823462 , H01L27/11524 , H01L27/11534 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/518 , H01L29/6659
摘要： A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.

7. 发明授权

US09472247B2 Memory, semiconductor device including the same, and method for testing the same 有权
标题翻译：存储器，包括其的半导体器件及其测试方法
公开(公告)号：US09472247B2
公开(公告)日：2016-10-18
申请号：US14621521
申请日：2015-02-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Cheng-Hsiung Kuo , Gu-Huan Li , Jih-Chen Wang , Chung-Chieh Chen
IPC分类号： G11C7/10 , G11C29/00 , G11C7/22 , G11C14/00
CPC分类号： G11C7/106 , G11C7/22 , G11C14/0054 , G11C14/0063 , G11C16/18 , G11C29/00 , G11C29/1201 , G11C29/48
摘要： A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.
摘要翻译：存储器包括第一存储单元，第二存储单元，锁存单元和开关单元。锁存单元具有真实节点和补码节点。开关单元响应于第一控制信号和第二控制信号，并且被配置为响应于第一控制信号将第一存储器单元连接到真实节点并且将第二存储器单元与补码节点断开连接，并且连接所述第二存储器单元发送到所述补码节点并且响应于所述第二控制信号而将所述第一存储器单元与所述真实节点断开。还公开了包括存储器的半导体器件。还公开了一种用于测试存储器的方法。

8. 发明申请

US20160111159A1 10T Non-Volatile Static Random-Access Memory 有权
标题翻译： 10T非易失性静态随机存取存储器
公开(公告)号：US20160111159A1
公开(公告)日：2016-04-21
申请号：US14886663
申请日：2015-10-19
申请人： Cypress Semiconductor Corporation
发明人： Joseph S. Tandingan , Jayant Ashokkumar , David Still , Jesse J. Siman
IPC分类号： G11C14/00 , G11C16/14 , G11C16/04
CPC分类号： G11C11/419 , G11C14/0063 , G11C16/0466
摘要： A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
摘要翻译：提供了包括nvSRAM单元阵列的存储器及其操作方法。每个nvSRAM单元包括易失性电荷存储电路，以及非易失性电荷存储电路，其包括正好一个非易失性存储器（NVM）元件，耦合到NVM元件的第一晶体管，通过该元件将数据真实耦合到易失性电荷存储电路耦合到所述NVM元件的第二晶体管，通过所述第二晶体管将所述数据的互补件耦合到所述易失性电荷存储电路;以及第三晶体管，所述NVM元件通过所述第三晶体管耦合到正电压电源线（VCCT）。在一个实施例中，第一晶体管耦合到NVM元件的第一节点，第二晶体管耦合到NVM元件的第二节点，第三晶体管耦合在第一节点和VCCT之间。还公开了其他实施例。

9. 发明授权

US09245627B2 Compact memory device including a SRAM memory plane and a non volatile memory plane, and operating methods 有权
标题翻译：包括SRAM存储器平面和非易失性存储器平面的紧凑型存储器件以及操作方法
公开(公告)号：US09245627B2
公开(公告)日：2016-01-26
申请号：US14296014
申请日：2014-06-04
申请人： STMicroelectronics (Rousset) SAS
发明人： François Tailliet , Marc Battista
IPC分类号： G11C14/00 , G11C16/04 , G11C5/02 , G11C16/20 , G11C11/404
CPC分类号： G11C16/0408 , G11C11/404 , G11C14/0018 , G11C14/0063 , G11C16/20
摘要： A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.
摘要翻译：存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。非易失性基本存储单元和可控互连级彼此连接。当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。

10. 发明申请

US20150371708A1 SRAM CELLS 有权
公开(公告)号：US20150371708A1
公开(公告)日：2015-12-24
申请号：US14767442
申请日：2014-02-06
申请人： SURECORE LIMITED
发明人： Andrew PICKERING
IPC分类号： G11C14/00 , G11C11/404 , G11C11/419
CPC分类号： G11C14/0063 , G11C8/14 , G11C11/404 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/418 , G11C11/419
摘要： There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.
摘要翻译：提供了包括多个存储单元组的存储器单元，每个存储单元组包括多个存储单元，每个存储单元通过相应的第一和第二存取晶体管可操作地连接到第一局部位线和第二局部位线，并且每个存储器单元与被配置为控制存储器单元的第一和第二存取晶体管的字线相关联。每个存储单元组的第一和第二局部位线通过相应的第一和第二组访问开关可操作地连接到相应的第一和第二列位线，第一组访问开关被配置为由第二列位线控制，以及第二组访问开关被配置为由第一列位线控制。

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